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27.3 Global name space of imported and exported functions</div>
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Every task or function imported to SystemVerilog must eventually resolve to a global symbol. Similarly, every task or function exported from SystemVerilog defines a global symbol. Thus the tasks and functions imported to and exported from SystemVerilog have their own global name space of linkage names, different from compilation- unit scope name space. Global names of imported and exported tasks and functions must be unique (no overloading is allowed ) and shall follow C conventions for naming; specifically, such names must start with a letter or underscore, and can be followed by alphanumeric characters or underscores. Exported and imported tasks and functions, however, can be declared with local SystemVerilog names. Import and export declarations allow users to specify a global name for a function in addition to its declared name. Should a global name clash with a SystemVerilog keyword or a reserved name, it shall take the form of an escaped identifier. The leading backslash ( \ ) character and the trailing white space shall be stripped off by the SystemVerilog tool to create the linkage identifier. Note that after this stripping, the linkage identifier so formed must comply with the normal rules for C identifier construction. If a global name is not explicitly given, it shall be the same as the SystemVerilog task or function name. For example: </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00965"><pre class="Element12">export &quot;DPI&quot; foo_plus = function \foo+ ; // &quot;foo+&quot; exported as &quot;foo_plus&quot;
export &quot;DPI&quot; function foo; // &quot;foo&quot; exported under its own name
import &quot;DPI&quot; init_1 = function void \init[1] (); // &quot;init_1&quot; is a linkage name
import &quot;DPI&quot; \begin = function void \init[2] (); // &quot;begin&quot; is a linkage name</pre></div></div>
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The same global task or function can be referred to in multiple import declarations in different scopes or/and with different SystemVerilog names, see Section 27.4.4.&nbsp;</p>
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Multiple export declarations are allowed with the same c_identifier, explicit or implicit, as long as they are in different scopes and have the same type signature (as defined in Section 27.4.4 for imported tasks and functions). Multiple export declarations with the same c_identifier in the same scope are forbidden.</p></div>
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