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<a href="#" onmousedown="showPopup(this, 'popup00361');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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17.13 并发断言</div>
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A property on its own is never evaluated for checking an expression. It must be used within a verification statement for this to occur. A verification statement states the verification function to be performed on the property. The statement can be one of the following:
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<li class="Element602">assert to specify the property as a checker to ensure that the property holds for the design</li>
<li class="Element602">assume to specify the property as an assumption for the environment</li>
<li class="Element602">cover to monitor the property evaluation for coverage</li>
</ul>A concurrent assertion statement can be specified in:
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<li class="Element602">an always block or initial block as a statement, wherever these blocks can appear</li>
<li class="Element602">a module</li>
<li class="Element602">an interface</li>
<li class="Element602">a program</li>
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<div class="Element13"><div class="Element12" id="code00743"><pre class="Element12">procedural_assertion_statement ::= // from Annex A.6.10
concurrent_assertion_statement
| immediate_assert_statement
concurrent_assertion_item ::= // from Annex A.2.10
[block_identifier :] concurrent_assertion_statement
concurrent_assertion_statement ::=
assert_property_statement
| assume_property_statement
| cover_property_statement
assert_property_statement::=
<strong><span style="color: #FF0000">assert property (</span></strong>property_spec<strong><span style="color: #FF0000">)</span></strong> action_block
assume_property_statement::=
<strong><span style="color: #FF0000">assume property (</span></strong>property_spec<strong><span style="color: #FF0000">);</span></strong>
cover_property_statement::=
<strong><span style="color: #FF0000">cover property (</span></strong>property_spec<strong><span style="color: #FF0000">)</span></strong> statement_or_null</pre></div></div>
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<strong>Syntax 17-16—Concurrent assert construct syntax (excerpt from Annex A)</strong></p><p class="Element10">
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The assert, assume or cover statements can be referenced by their optional name. A hierarchical name can be used consistent with the SystemVerilog naming conventions. When a name is not provided, a tool shall assign a name to the statement for the purpose of reporting. Assertion control system tasks are described in Section 23.9.</p></div>
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描述 </div></td></tr><tr>
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The assert statement is used to enforce a property as a checker. When the property for the assert statement is evaluated to be true, the pass statements of the action block are executed. Otherwise, the fail statements of the action_block are executed. For example, </div></td></tr><tr>
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The purpose of the assume statement is to allow properties to be considered as assumptions for formal analysis as well as for dynamic simulation tools. When a property is assumed, the tools constrain the environment so that the property holds.<br><br>For formal analysis, there is no obligation to verify that the assumed properties hold. An assumed property can be considered as a hypothesis to prove the asserted properties.<br><br>For simulation, the environment must be constrained such that the properties that are assumed shall hold. Like an assert property, an assumed property must be checked and reported if it fails to... <a href="00159.html" target="topic">more</a> </div></td></tr><tr>
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To monitor sequences and other behavioral aspects of the design for coverage, the same syntax is used with the cover statement. The tools can gather information about the evaluation and report the results at the end of simulation. When the property for the cover statement is successful, the pass statements can specify a coverage function, such as monitoring all paths for a sequence. The pass statement shall not include any concurrent assert, assume or cover statement.<br><br>Coverage results are divided into two: coverage for properties, coverage for sequences.<br><br>For sequence coverage, the statement appears as: </div></td></tr><tr>
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A concurrent assertion statement can be used outside of a procedural context. It can be used within a module, an interface, or a program. A concurrent assertion statement is an assert, an assume, or a cover statement.Such a concurrent assertion statement uses the always semantics.<br><br>The following two forms are equivalent: </div></td></tr><tr>
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A concurrent assertion statement can also be embedded in a procedural block. For example: </div></td></tr></table></div></div>
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