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<a href="#" onmousedown="showPopup(this, 'popup00386');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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18.11.2 Instantiation using named port connections</div>
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Verilog has always permitted instantiation of modules using named port connections as shown in the alu_accum2 module example. </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00820"><pre class="Element12">module alu_accum2 (
output [15:0] dataout,
input [7:0] ain, bin,
input [2:0] opcode,
input clk, rst_n);
wire [7:0] alu_out;
alu alu (.alu_out(alu_out), .zero(),
.ain(ain), .bin(bin), .opcode(opcode));
accum accum (.dataout(dataout[7:0]), .datain(alu_out),
.clk(clk), .rst_n(rst_n));
xtend xtend (.dout(dataout[15:8]), .din(alu_out[7]),
.clk(clk), .rst_n(rst_n));
endmodule</pre></div></div>
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Named port connections do not have to be ordered the same as the ports of the instantiated module. The variables connected to the instance ports must be the same size or a port-size mismatch warning shall be reported.</p></div>
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