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<a href="#" onmousedown="showPopup(this, 'popup00638');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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附录A 形式语法</div>
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The formal syntax of SystemVerilog is described using Backus-Naur Form (BNF). The conventions used are:
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<li class="Element600">Keywords and punctuation are in bold text.</li>
<li class="Element600">Syntactic categories are named in non-bold text.</li>
<li class="Element600">A vertical bar (|) separates alternatives.</li>
<li class="Element600">Square brackets ([]) enclose optional items.</li>
<li class="Element600">Braces ({}) enclose items which can be repeated zero or more times.</li>
</ul>The full syntax and semantics of Verilog and SystemVerilog are not described solely using BNF. The normative text description contained within the chapters of the IEEE 1364-2001 Verilog standard and this SystemVerilog document provide additional details on the syntax and semantics described in this BNF.</p></div>
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<li value="1" class="Element600">Embedded spaces are illegal.</li>
<li value="2" class="Element600">A simple_identifier, c_identifier, and arrayed_reference shall start with an alpha or underscore ( _ ) character, shall have at least one character, and shall not have any spaces.</li>
<li value="3" class="Element600">The $ character in a system_tf_identifier shall not be followed by white_space. A system_tf_identifier shall not be escaped.</li>
<li value="4" class="Element600">End of file.</li>
<li value="5" class="Element600">The unsigned number or fixed point number in time_literal shall not be followed by a white_space.</li>
<li value="6" class="Element600">implicit_class_handle shall only appear within the scope of a class_declaration or out-of-block method declaration.</li>
<li value="7" class="Element600">In any one declaration, only one of protected or local is allowed, only one of rand or... <a href="00619.html" target="topic">more</a> </div></td></tr></table></div></div>
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