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<a href="00883.html" target="topic">附录E DPI C-layer</a>, <a href="01042.html" target="topic">主题</a></div>
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<a href="#" onmousedown="showPopup(this, 'popup00818');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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E.11 Open arrays</div>
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Formal arguments specified as open arrays allows passing actual arguments of different sizes (i.e., different range and/or different number of elements), which facilitates writing more general C code that can handle SystemVerilog arrays of different sizes. The elements of an open array can be accessed in C by using the same range of indices and the same indexing as in SystemVerilog. Plus, inquiries about the dimensions and the original boundaries of SystemVerilog actual arguments are supported for open arrays. </p>
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NOTE—Both packed and unpacked array dimensions can be unsized. </p>
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All formal arguments declared in SystemVerilog as open arrays are passed by handle (type svOpenArray- Handle), regardless of the direction of a SystemVerilog formal argument. Such arguments are accessible via interface functions.</p></div>
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描述 </div></td></tr><tr>
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<a href="00744.html" target="topic">E.11.1 Actual ranges</a> </div></td><td class="Element206" valign="top" width="50%">
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The formal arguments defined as open arrays have the size and ranges of the actual argument, as determined on a per-call basis. The programmer shall always have a choice whether to specify a formal argument as a sized array or as an open (unsized) array.<br><br>In the former case, all indices are normalized on the C side (i.e., 0 and up) and the programmer needs to know the size of an array and be capable of determining how the ranges of the actual argument map onto C-style ranges (see Annex E.6.6).<br><br>Tip: programmers can decide to use [n:0]name[0:k] style ranges... <a href="00744.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00747.html" target="topic">E.11.2 Array querying functions</a> </div></td><td class="Element206" valign="top" width="50%">
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These functions are modelled upon the SystemVerilog array querying functions and use the same semantics (see Section 23.7).<br><br>If the dimension is 0, then the query refers to the packed part (which is one-dimensional) of an array, and dimensions > 0 refer to the unpacked part of an array. </div></td></tr><tr>
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<a href="00748.html" target="topic">E.11.3 Access functions</a> </div></td><td class="Element206" valign="top" width="50%">
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Similarly to sized arrays, there are functions for copying data between the simulator representation and the canonical representation and to obtain the actual address of SystemVerilog data object or of an individual element of an unpacked array. This information might be useful for simulator-specific tuning of the application. Depending on the type of an element of an unpacked array, different access methods shall be used when working with elements.
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<li class="Element600">Packed arrays ( bit or logic) are accessed via copying to or from the canonical representation.</li>
<li class="Element600">Scalars (1-bit value of type bit or logic) are accessed (read or written) directly.</li>
<li class="Element600">Other... <a href="00748.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00749.html" target="topic">E.11.4 Access to the actual representation</a> </div></td><td class="Element206" valign="top" width="50%">
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The following functions provide an actual address of the whole array or of its individual elements. These functions shall be used for accessing elements of arrays of types compatible with C. These functions are also useful for vendors, because they provide access to the actual representation for all types of arrays.<br><br>If the actual layout of the SystemVerilog array passed as an argument for an open unpacked array is different than the C layout, then it is not possible to access such an array as a whole; therefore, the address and size of such an array shall be undefined (zero... <a href="00749.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00750.html" target="topic">E.11.5 Access to elements via canonical representation</a> </div></td><td class="Element206" valign="top" width="50%">
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The following functions copy a single vector from a canonical representation to an element of an open array or other way round. The element of an array is identified by indices, bound by the ranges of the actual argument, i.e., the original SystemVerilog ranges are used for indexing. </div></td></tr><tr>
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<a href="00751.html" target="topic">E.11.6 Access to scalar elements (bit and logic)</a> </div></td><td class="Element206" valign="top" width="50%">
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Another group of functions is needed for scalars (i.e., when an element of an array is a simple scalar, bit, or logic): </div></td></tr><tr>
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<a href="00752.html" target="topic">E.11.7 Access to array elements of other types</a> </div></td><td class="Element206" valign="top" width="50%">
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If an array’s elements are of a type compatible with C, there is no need to use canonical representation. In such situations, the elements are accessed via pointers, i.e., the actual address of an element shall be computed first and then used to access the desired element. </div></td></tr><tr>
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<a href="00753.html" target="topic">E.11.8 Example 4— two-dimensional open array</a> </div></td><td class="Element206" valign="top" width="50%">
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SystemVerilog: </div></td></tr><tr>
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<a href="00754.html" target="topic">E.11.9 Example 5 — open array</a> </div></td><td class="Element206" valign="top" width="50%">
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SystemVerilog: </div></td></tr><tr>
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<a href="00745.html" target="topic">E.11.10 Example 6 — access to packed arrays</a> </div></td><td class="Element206" valign="top" width="50%">
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SystemVerilog: </div></td></tr><tr>
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<a href="00746.html" target="topic">E.11.11 Example 7 — binary compatible calls of exported functions</a> </div></td><td class="Element206" valign="top" width="50%">
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This example demonstrates the source compatibility include file svdpi_src.h is not needed if a C function dynamically allocates the data structure for simulator representation of a packed array to be passed to an exported SystemVerilog function.<br><br>SystemVerilog: </div></td></tr></table></div></div>
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