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18.11 模块实例</div>
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<div class="Element13"><div class="Element12" id="code00817"><pre class="Element12">module_instantiation ::= // from Annex A.4.1.1
module_identifier [parameter_value_assignment] hierarchical_instance {, hierarchical_instance};
parameter_value_assignment ::= # ( list_of_parameter_assignments )
list_of_parameter_assignments ::=
ordered_parameter_assignment { , ordered_parameter_assignment }
| named_parameter_assignment { , named_parameter_assignment }
ordered_parameter_assignment ::= param_expression
named_parameter_assignment ::= . parameter_identifier ( [ param_expression ] )
hierarchical_instance ::= name_of_instance ( [ list_of_port_connections ] )
name_of_instance ::= instance_identifier { unpacked_dimension }
list_of_port_connections17 ::=
ordered_port_connection { , ordered_port_connection }
| named_port_connection { , named_port_connection }
ordered_port_connection ::= { attribute_instance } [ expression ]
named_port_connection ::=
{ attribute_instance } . port_identifier [ ( [ expression ] ) ]
| { attribute_instance } .*
param_expression ::= mintypmax_expression | data_type // from Annex A.8.3</pre></div></div>
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<strong>Syntax 18-5—Module instance syntax (excerpt from Annex A)</strong></p><p class="Element10">
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A module can be used (instantiated) in two ways, hierarchical or top level. Hierarchical instantiation allows more than one instance of the same type. The module name can be a module previously declared or one declared later. Actual parameters can be named or ordered. Port connections can be named, ordered or implicitly connected. They can be nets, variables, or other kinds of interfaces, events, or expressions. See below for the connection rules. </p>
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Consider an ALU accumulator (alu_accum) example module that includes instantiations of an ALU module, an accumulator register (accum) module and a sign-extension (xtend) module. The module headers for the three instantiated modules are shown in the following example code. </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00818"><pre class="Element12">module alu (
output reg [7:0] alu_out,
output reg zero,
input [7:0] ain, bin,
input [2:0] opcode);
// RTL code for the alu module
endmodule
module accum (
output reg [7:0] dataout,
input [7:0] datain,
input clk, rst_n);
// RTL code for the accumulator module
endmodule
module xtend (
output reg [7:0] dout,
input din,
input clk, rst_n);
// RTL code for the sign-extension module
endmodule</pre></div></div>
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描述 </div></td></tr><tr>
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<a href="00191.html" target="topic">18.11.1 Instantiation using positional port connections</a> </div></td><td class="Element206" valign="top" width="50%">
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Verilog has always permitted instantiation of modules using positional port connections, as shown in the alu_accum1 module example, below. </div></td></tr><tr>
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<a href="00192.html" target="topic">18.11.2 Instantiation using named port connections</a> </div></td><td class="Element206" valign="top" width="50%">
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Verilog has always permitted instantiation of modules using named port connections as shown in the alu_accum2 module example. </div></td></tr><tr>
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<a href="00193.html" target="topic">18.11.3 Instantiation using implicit .name port connections</a> </div></td><td class="Element206" valign="top" width="50%">
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SystemVerilog adds the capability to implicitly instantiate ports using a .name syntax if the instance-port name and size match the connecting variable-port name and size. This enhancement eliminates the requirement to list a port name twice when the port name and signal name are the same, while still listing all of the ports of the instantiated module for documentation purposes.<br><br>In the following alu_accum3 example, all of the ports of the instantiated alu module match the names of the variables connected to the ports, except for the unconnected zero port, which is listed using a named port connection, showing that... <a href="00193.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00194.html" target="topic">18.11.4 Instantiation using implicit .* port connections</a> </div></td><td class="Element206" valign="top" width="50%">
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SystemVerilog adds the capability to implicitly instantiate ports using a .* syntax for all ports where the instance-port name and size match the connecting variable-port name and size. This enhancement eliminates the requirement to list any port where the name and size of the connecting variable match the name and size of the instance port. This implicit port connection style is used to indicate that all port names and sizes match the connections where emphasis is placed only on the exception ports. The implicit .* port connection syntax can greatly facilitate rapid block-level testbench generation where all of the testbench... <a href="00194.html" target="topic">more</a> </div></td></tr></table></div></div>
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