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<a href="00866.html" target="topic">第十九章 接口</a>, <a href="00961.html" target="topic">主题</a></div>
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<a href="#" onmousedown="showPopup(this, 'popup00417');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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19.8 虚拟接口</div>
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Virtual interfaces provide a mechanism for separating abstract models and test programs from the actual signals that make up the design. A virtual interface allows the same subprogram to operate on different portions of a design, and to dynamically control the set of signals associated with the subprogram. Instead of referring to the actual set of signals directly, users are able to manipulate a set of virtual signals. Changes to the underlying design do not require the code using virtual interfaces to be re-written. By abstracting the connectivity and functionality of a set of blocks, virtual interfaces promote code-reuse. </p>
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A virtual interface is a variable that represents an interface instance. The syntax to declare a virtual interface variable is given below. </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00854"><pre class="Element12">virtual_interface_declaration ::= // from Annex A.2.9
<strong><span style="color: #FF0000">virtual</span></strong> [<strong><span style="color: #FF0000">interface</span></strong>] interface_identifier list_of_virtual_interface_decl<strong><span style="color: #FF0000">;</span></strong>
list_of_virtual_interface_decl ::= // from Annex A.2.3
variable_identifier [<strong><span style="color: #FF0000">=</span></strong> interface_instance_identifier
{<strong><span style="color: #FF0000">,</span></strong> variable_identifier [<strong><span style="color: #FF0000">=</span></strong> interface_instance_identifier]}
data_declaration ::= // from Annex A.2.1.3
...
| virtual_interface_declaration
data_type ::= // from Annex A.2.2.1
...
| <strong><span style="color: #FF0000">virtual</span></strong> [<strong><span style="color: #FF0000">interface</span></strong>] interface_identifier</pre></div></div>
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<strong>Syntax 19-3—virtual interface declaration syntax (excerpt from Annex A)</strong></p><p class="Element10">
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Virtual interface variables can be passed as arguments to tasks, functions, or methods. A single virtual interface variable can thus represent different interface instances at different times throughout the simulation. A virtual interface must be initialized before it can be used; it has the value null before it is initialized. Attempting to use an uninitialized virtual interface shall result in a fatal run-time error. </p>
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Only the following operations are directly allowed on virtual interface variables:
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<li class="Element606">Assignment ( = ) to:
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<li class="Element607">another virtual interface of the same type</li>
<li class="Element607">an interface instance of the same type</li>
<li class="Element607">the special constant null</li>
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<li class="Element606">Equality ( == ) and inequality ( != ) with:
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<li class="Element607">another virtual interface of the same type</li>
<li class="Element607">an interface instance of the same type</li>
<li class="Element607">the special constant null</li>
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</ul>Virtual interfaces shall not be used as ports, interface items, or as members of unions. </p>
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Once a virtual interface has been initialized, all the components of the underlying interface instance are directly available to the virtual interface via the dot notation. These components can only be used in procedural statements; they cannot be used in continuous assignments or sensitivity lists. In order for a net to be driven via a virtual interface, the interface itself must provide a procedural means to do so. This can be accomplished either via a clocking block or by including a driver that is updated by a continuous assignment from a variable within the interface. </p>
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Virtual interfaces can be declared as class properties, which can be initialized procedurally or by an argument to new(). This allows the same virtual interface to be used in different classes. The following example shows how the same transactor class can be used to interact with various different devices. </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00855"><pre class="Element12">interface SBus; // A Simple bus interface
logic req, grant;
logic [7:0] addr, data;
endinterface
class SBusTransctor; // SBus transactor class
virtual SBus bus; // virtual interface of type Sbus
function new( virtual SBus s );
bus = s; // initialize the virtual interface
endfunction
task request(); // request the bus
bus.req <= 1’b1;
endtask
task wait_for_bus(); // wait for the bus to be granted
@(posedge bus.grant);
endtask
endclass
module devA( Sbus s ) ... endmodule // devices that use SBus
module devB( Sbus s ) ... endmodule
module top;
SBus s[1:4] (); // instantiate 4 interfaces
devA a1( s[1] ); // instantiate 4 devices
devB b1( s[2] );
devA a2( s[3] );
devB b2( s[4] );
initial begin
SbusTransactor t[1:4]; // create 4 bus-transactors and bind
t[1] = new( s[1] );
t[2] = new( s[2] );
t[3] = new( s[3] );
t[4] = new( s[4] );
// test t[1:4]
end
endmodule</pre></div></div>
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In the preceding example, the transaction class SbusTransctor is a simple reusable component. It is written without any global or hierarchical references, and is unaware of the particular device with which it will interact. Nevertheless, the class can interact with any number of devices (4 in the example) that adhere to the interface’s protocol.</p></div>
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描述 </div></td></tr><tr>
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<a href="00233.html" target="topic">19.8.1 Virtual interfaces and clocking blocks</a> </div></td><td class="Element206" valign="top" width="50%">
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Clocking blocks and interfaces can be combined to represent the interconnect between synchronous blocks. Moreover, because clocking blocks provide a procedural mechanism to assign values to both nets and variables, they are ideally suited to be used by virtual interfaces. For example: </div></td></tr><tr>
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<a href="00234.html" target="topic">19.8.2 Virtual interfaces modports and clocking blocks</a> </div></td><td class="Element206" valign="top" width="50%">
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As shown in the example above, once a virtual interface is declared, its clocking block can be referenced using dot-notation. However, this only works for interfaces with no modports. Typically, a device under test and its testbench exhibit modport direction. This common case can be handled by including the clocking in the corresponding modport as described in Section 19.4.5.<br><br>The example below shows how modports used in conjunction with virtual interfaces facilitate the creation of abstract synchronous models. </div></td></tr></table></div></div>
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