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<a href="00871.html" target="topic">第十五章 时钟控制块</a></div>
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<a href="#" onmousedown="showPopup(this, 'popup00307');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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15.8 接口与时钟控制块</div>
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一个时钟控制块封装了一组共享一个基本时钟的信号,因此使用一个SystemVerilog接口说明一个时钟控制块能够显著地减少连接测试平台所需代码的数目。此外,由于测试平台内时钟控制块中信号方向是有关测试平台而不是被测设计的,一个<span style="color: #0000FF">modport</span>声明可以恰当地描述这两个方向。一个测试平台程序可以包含在一个程序当中,并且它的端口可以是接口,这个接口对应于每个时钟控制块中声明的信号。从测试平台这一侧(也就是<span class="Element146"><span style="color: #0000FF">modport</span> test</span>)看接口中的连线应该与时钟控制块中声明的方向相同,而从被测设计来看则具有相反的方向(也就是<span class="Element146"><span style="color: #0000FF">modport</span> dut</span>)。 </p>
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</p>
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例如,前面的例子可以使用接口按如下的方式重新编写: </p><div class="Element170">
<a href="#" onclick="CopyElementToClipboard('code00539');">Copy Code</a></div>
<div class="Element13"><div class="Element12" id="code00539"><pre class="Element12"><span style="color: #0000FF">interface</span> bus_A <span style="color: #800080">(</span><span style="color: #0000FF">input</span> clk<span style="color: #800080">);</span>
<span style="color: #0000FF">logic</span> <span style="color: #800080">[</span><span style="color: #FF0000">15</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> data<span style="color: #800080">;</span>
<span style="color: #0000FF">logic</span> write<span style="color: #800080">;</span>
<span style="color: #0000FF">modport</span> test <span style="color: #800080">(</span><span style="color: #0000FF">input</span> data<span style="color: #800080">,</span> <span style="color: #0000FF">output</span> write<span style="color: #800080">);</span>
<span style="color: #0000FF">modport</span> dut <span style="color: #800080">(</span><span style="color: #0000FF">output</span> data<span style="color: #800080">,</span> <span style="color: #0000FF">input</span> write<span style="color: #800080">);</span>
<span style="color: #0000FF">endinterface</span>
<span style="color: #0000FF">interface</span> bus_B <span style="color: #800080">(</span><span style="color: #0000FF">input</span> clk<span style="color: #800080">);</span>
<span style="color: #0000FF">logic</span> <span style="color: #800080">[</span><span style="color: #FF0000">8</span><span style="color: #800080">:</span><span style="color: #FF0000">1</span><span style="color: #800080">]</span> cmd<span style="color: #800080">;</span>
<span style="color: #0000FF">logic</span> enable<span style="color: #800080">;</span>
<span style="color: #0000FF">modport</span> test <span style="color: #800080">(</span><span style="color: #0000FF">input</span> enable<span style="color: #800080">);</span>
<span style="color: #0000FF">modport</span> dut <span style="color: #800080">(</span><span style="color: #0000FF">output</span> enable<span style="color: #800080">);</span>
<span style="color: #0000FF">endinterface</span>
<span style="color: #0000FF">program</span> test<span style="color: #800080">(</span>bus_A<span style="color: #800080">.</span>test a<span style="color: #800080">,</span> bus_B<span style="color: #800080">.</span>test b<span style="color: #800080">);</span>
<span style="color: #0000FF">clocking</span> cd1 <span style="color: #800080">@(</span><span style="color: #0000FF">posedge</span> a<span style="color: #800080">.</span>clk<span style="color: #800080">);</span>
<span style="color: #0000FF">input</span> a<span style="color: #800080">.</span>data<span style="color: #800080">;</span>
<span style="color: #0000FF">output</span> a<span style="color: #800080">.</span>write<span style="color: #800080">;</span>
<span style="color: #0000FF">inout</span> state <span style="color: #800080">= </span>top<span style="color: #800080">.</span>cpu<span style="color: #800080">.</span>state<span style="color: #800080">;</span>
<span style="color: #0000FF">endclocking</span>
<span style="color: #0000FF"> clocking</span> cd2 <span style="color: #800080">@(</span><span style="color: #0000FF">posedge</span> b<span style="color: #800080">.</span>clk<span style="color: #800080">);</span>
<span style="color: #0000FF">input</span> <span style="color: #800080">#</span><span style="color: #FF0000">2</span> <span style="color: #0000FF">output</span> <span style="color: #800080">#</span><span style="color: #FF0000">4</span><span style="color: #0000FF">ps</span> b<span style="color: #800080">.</span>cmd<span style="color: #800080">;</span>
<span style="color: #0000FF">input</span> b<span style="color: #800080">.</span>enable<span style="color: #800080">;</span>
<span style="color: #0000FF">endclocking</span>
<span style="color: #0000FF"> initial begin</span>
<span style="color: #008000">// 程序从这里开始</span>
...
<span style="color: #008000">// 用户可以访问cd1.a.data,cd2.b.cmd等等</span>
<span style="color: #0000FF">end</span>
<span style="color: #0000FF">endprogram</span></pre></div></div>
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</p>
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<span class="Element146">test</span>模块可以被实例化并按如下方式连接: </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00540"><pre class="Element12"><span style="color: #0000FF">module</span> top<span style="color: #800080">;</span>
<span style="color: #0000FF">logic</span> phi1<span style="color: #800080">,</span> phi2<span style="color: #800080">;</span>
bus_A a<span style="color: #800080">(</span>phi1<span style="color: #800080">);</span>
bus_B b<span style="color: #800080">(</span>phi2<span style="color: #800080">);</span>
test main<span style="color: #800080">(</span>a<span style="color: #800080">, </span>b<span style="color: #800080">);</span>
cpu cpu1<span style="color: #800080">(</span>a<span style="color: #800080">);</span>
mem mem1<span style="color: #800080">(</span>b<span style="color: #800080">);</span>
<span style="color: #0000FF">endmodule</span></pre></div></div>
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</p>
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作为选择,在上面的test程序中,时钟控制块可以使用接口和层次化表达式按如下方式编写: </p><div class="Element170">
<a href="#" onclick="CopyElementToClipboard('code00541');">Copy Code</a></div>
<div class="Element13"><div class="Element12" id="code00541"><pre class="Element12"><span style="color: #0000FF">clocking</span> cd1 <span style="color: #800080">@(</span><span style="color: #0000FF">posedge</span> a<span style="color: #800080">.</span>clk<span style="color: #800080">);</span>
<span style="color: #0000FF">input</span> data <span style="color: #800080">=</span> a<span style="color: #800080">.</span>data<span style="color: #800080">;</span>
<span style="color: #0000FF">output</span> write <span style="color: #800080">=</span> a<span style="color: #800080">.</span>write<span style="color: #800080">;</span>
<span style="color: #0000FF">inout</span> state <span style="color: #800080">= </span>top<span style="color: #800080">.</span>cpu<span style="color: #800080">.</span>state<span style="color: #800080">;</span>
<span style="color: #0000FF">endclocking</span>
<span style="color: #0000FF">clocking</span> cd2 <span style="color: #800080">@(</span><span style="color: #0000FF">posedge</span> b<span style="color: #800080">.</span>clk<span style="color: #800080">);</span>
<span style="color: #0000FF">input</span> <span style="color: #800080">#</span><span style="color: #FF0000">2</span> <span style="color: #0000FF">output</span> <span style="color: #800080">#</span><span style="color: #FF0000">4</span><span style="color: #0000FF">ps</span> cmd <span style="color: #800080">=</span> b<span style="color: #800080">.</span>cmd<span style="color: #800080">;</span>
<span style="color: #0000FF">input</span> enable <span style="color: #800080">=</span> b<span style="color: #800080">.</span>enable<span style="color: #800080">;</span>
<span style="color: #0000FF">endclocking</span></pre></div></div>
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这就使得我们能够使用较短的名字(cd1.data, cd2.cmd, …)来替代较长的接口语法(cd1.a.data, cd2.b.cmd,…)。</p></div>
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