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<a href="#" onmousedown="showPopup(this, 'popup00115');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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第六章 属性</div>
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描述 </div></td></tr><tr>
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<a href="00552.html" target="topic">6.1 简介（一般信息）</a> </div></td><td class="Element206" valign="top" width="50%">
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在Verilog-2001中，用户可以为Verilog对象（例如模块、实例、wire等）加入命名的属性。属性还可以在扩展的SystemVerilog结构中指定，并作为BNF的一部分（参见<a href="00879.html" target="topic">附录A</a>）。SystemVerilog还为属性定义了一个缺省的数据类型。 </div></td></tr><tr>
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一个没有值的属性的缺省类型是<span style="color: #0000FF">bit</span>，它的值为<span style="color: #FF0000">1</span>。另外，属性接受表达式的类型。 </div></td></tr></table></div></div>
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