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<title>27.4 导入的任务和函数</title>
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<a href="00851.html" target="topic">第二十七章 直接编程接口(DPI)</a>, <a href="00978.html" target="topic">主题</a></div>
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<a href="#" onmousedown="showPopup(this, 'popup00488');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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27.4 导入的任务和函数</div>
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导入函数的使用与SystemVerilog原生函数类似。</p></div>
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<a href="00851.html" target="topic">第二十七章 直接编程接口(DPI)</a></p></div>
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描述&nbsp;</div></td></tr><tr>
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<a href="00305.html" target="topic">27.4.1 Required properties of imported tasks and functions — semantic constraints</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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This section defines the semantic constraints imposed on imported tasks or functions. Some semantic restrictions are shared by all imported tasks or functions. Other restrictions depend on whether the special properties pure (see Section 27.4.2) or context (see Section 27.4.3) are specified for an imported task or function. A SystemVerilog compiler is not able to verify that those restrictions are observed and if those restrictions are not satisfied, the effects of such imported task or function calls can be unpredictable.&nbsp;</div></td></tr><tr>
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<a href="00312.html" target="topic">27.4.2 Pure functions</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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A pure function call can be safely eliminated if its result is not needed or if the previous result for the same values of input arguments is available somehow and can be reused without needing to recalculate. Only nonvoid functions with no output or inout arguments can be specified as pure. Functions specified as pure shall have no side effects whatsoever; their results need to depend solely on the values of their input arguments. Calls to such functions can be removed by SystemVerilog compiler optimizations or replaced with the values previously computed for the same values of the input arguments.... <a href="00312.html" target="topic">more</a>&nbsp;</div></td></tr><tr>
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<a href="00313.html" target="topic">27.4.3 Context tasks and functions</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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Some DPI imported tasks or functions require that the context of their call is known. It takes special instrumentation of their call instances to provide such context; for example, an internal variable referring to the “current instance” might need to be set. To avoid any unnecessary overhead, imported task or function calls in SystemVerilog code are not instrumented unless the imported task or function is specified as context.<br><br>All DPI exported tasks or functions require that the context of their call is known. This occurs since SystemVerilog task or function declarations always occur in instantiable scopes, hence allowing a multiplicity... <a href="00313.html" target="topic">more</a>&nbsp;</div></td></tr><tr>
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<a href="00314.html" target="topic">27.4.4 Import declarations</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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Each imported task or function shall be declared. Such declaration are referred to as import declarations. The syntax of an import declaration is similar to the syntax of SystemVerilog task or function prototypes (see Section 10.5).<br><br>Imported tasks or functions are similar to SystemVerilog tasks or functions. Imported tasks or functions can have zero or more formal input, output, and inout arguments. Imported functions can return a result or be defined as void functions. Imported tasks never return a result, and thus are always declared in foreign code as void functions. &nbsp;</div></td></tr><tr>
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<a href="00315.html" target="topic">27.4.5 Function result</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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Function result types are restricted to small values. The following SystemVerilog data types are allowed for imported function results:
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<li class="Element609">void, byte, shortint, int, longint, real, shortreal, chandle, and string</li>
<li class="Element609">packed bit arrays up to 32 bits and all types that are eventually equivalent to packed bit arrays up to 32 bits</li>
<li class="Element609">scalar values of type bit and logic</li>
</ul>The same restrictions apply for the result types of exported functions.&nbsp;</div></td></tr><tr>
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<a href="00316.html" target="topic">27.4.6 形式参数的类型</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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A rich subset of SystemVerilog data types is allowed for formal arguments of import and export tasks or functions. Generally, C compatible types, packed types and user defined types built of types from these two categories can be used for formal arguments of DPI tasks or functions. The set of permitted types is defined inductively.<br><br>The following SystemVerilog types are the only permitted types for formal arguments of import and export tasks or functions:
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<li class="Element609">void, byte, shortint, int, longint, real, shortreal, chandle, and string</li>
<li class="Element609">scalar values of type bit and logic</li>
<li class="Element609">packed one dimensional arrays of type bit and logic... <a href="00316.html" target="topic">more</a>&nbsp;</div></td></tr></table></div></div>
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<a href="00851.html" target="topic">第二十七章 直接编程接口(DPI)</a>, <a href="00978.html" target="topic">主题</a></div>
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