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<a href="#" onmousedown="showPopup(this, 'popup00369');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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17.15 将特性绑定到作用域或实例</div>
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To facilitate verification separate from the design, it is possible to specify properties and bind them to specific modules or instances. The following are the goals of providing this feature:
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<li class="Element602">It allows verification engineers to verify with minimum changes to the design code/files.</li>
<li class="Element602">It allows a convenient mechanism to attach verification IP to a module or an instance.</li>
<li class="Element602">No semantic changes to the assertions are introduced due to this feature. It is equivalent to writing properties external to a module, using hierarchical path names.</li>
</ul>With this feature, a user can bind a module, interface, or program instance to a module or a module instance. </p>
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The syntax of the bind construct is: </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00785"><pre class="Element12">bind_directive ::= <strong><span style="color: #FF0000">bind</span></strong> hierarchical_identifier constant_select bind_instantiation<strong><span style="color: #FF0000">;</span></strong>
<strong><span style="color: #FF0000"> </span></strong>// from Annex A.1.5
bind_instantiation ::=
program_instantiation
| module_instantiation
| interface_instantiation</pre></div></div>
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<strong>Syntax 17-17—bind construct syntax (excerpt from Annex A)</strong></p><p class="Element10">
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The bind directive can be specified in
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<li class="Element602">a module</li>
<li class="Element602">an interface</li>
<li class="Element602">a compilation-unit scope</li>
</ul>A program block contains non-design code (either testbench or properties) and executes in the Reactive region, as explained in Section 16. </p>
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Example of binding a program instance to a module: </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00786"><pre class="Element12">bind cpu fpu_props fpu_rules_1(a,b,c);</pre></div></div>
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Where:
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<li class="Element602">cpu is the name of module.</li>
<li class="Element602">fpu_props is the name of the program containing properties.</li>
<li class="Element602">fpu_rules_1 is the program instance name.</li>
<li class="Element602">Ports (a, b,c) get bound to signals (a,b,c) of module cpu.</li>
<li class="Element602">Every instance of cpu gets the properties.</li>
</ul>Example of binding a program instance to a specific instance of a module: </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00787"><pre class="Element12">bind cpu1 fpu_props fpu_rules_1(a,b,c);</pre></div></div>
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By binding a program to a module or an instance, the program becomes part of the bound object. The names of assertion-related declarations can be referenced using the SystemVerilog hierarchical naming conventions. </p>
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Binding of a module instance or an interface instance works the same way as described for programs above. </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00788"><pre class="Element12">interface range (input clk,enable, input int minval,expr);
property crange_en;
@(posedge clk) enable |-> (minval <= expr);
endproperty
range_chk: assert property (crange_en);
endinteface
bind cr_unit range r1(c_clk,c_en,v_low,(in1&&in2));</pre></div></div>
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In this example, interface range is instantiated in the module cr_unit. Effectively, every instance of module cr_unit shall contain the interface instance r1.</p></div>
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