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<a href="#" onmousedown="showPopup(this, 'popup00771');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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E.5 Semantic constraints</div>
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Formal and actual arguments of both imported tasks or functions and exported tasks or functions are bound by the principle “What You Specify Is What You Get.” This principle is binding both for the caller and for the callee, in C code and in SystemVerilog code. For the callee, it guarantees the actual arguments are as specified for the formal ones. For the caller, it means the function call arguments shall conform with the types of the formal arguments, which might require type-coercion on the caller side. </p>
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Another way to state this is that no compiler (either C or SystemVerilog) can make argument coercions between a caller’s declared formals and the callee’s declared the formals. This is because the callee’s formal arguments are declared in a different language than the caller’s formal arguments; hence there is no visible relationship between the two sets of formals. Users are expected to understand all argument relationships and provide properly matched types on both sides of the interface (see Annex E.6.2). </p>
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In SystemVerilog code, the compiler can change the formal arguments of a native SystemVerilog task or function and modify its code accordingly, because of optimizations, compiler pragmas, or command line switches. The situation is different for imported tasks and functions. A SystemVerilog compiler cannot modify the C code, perform any coercions, or make any changes whatsoever to the formal arguments of an imported task or function. </p>
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A SystemVerilog compiler shall provide any necessary coercions for the actual arguments of every imported task and function call. For example, a SystemVerilog compiler might truncate or extend bits of a packed array if the widths of the actual and formal arguments are different. Similarly, a C compiler can provide coercion for C types based on the relationship of the arguments in the exported task’s and function’s C prototype (formals) and the exported task’s and function’s C call site (actuals). However, a C compiler cannot provide such coercion for SystemVerilog types. </p>
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Thus, in each case of an inter-language function call, either C to SystemVerilog or SystemVerilog to C, the compilers expect but cannot enforce that the types on either side are compatible. It is therefore the user’s responsibility to ensure that the imported/exported function types exactly match the types of the corresponding tasks or functions in the foreign language.</p></div>
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<a href="00763.html" target="topic">E.5.1 Types of formal arguments</a> </div></td><td class="Element206" valign="top" width="50%">
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The principle “What You Specify Is What You Get” guarantees the types of formal arguments of imported functions — an actual argument is guaranteed to be of the type specified for the formal argument, with the exception of open arrays (for which unspecified ranges are statically unknown). Formal arguments, other than open arrays, are fully defined by imported declaration; they shall have ranges of packed or unpacked arrays exactly as specified in the imported declaration. Only the SystemVerilog declaration site of the imported function is relevant for such formal arguments.<br><br>Formal arguments defined as open arrays have the size and... <a href="00763.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00764.html" target="topic">E.5.2 input arguments</a> </div></td><td class="Element206" valign="top" width="50%">
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Formal arguments specified in SystemVerilog as input must not be modified by the foreign language code. See also Section 27.4.1.2. </div></td></tr><tr>
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<a href="00765.html" target="topic">E.5.3 output arguments</a> </div></td><td class="Element206" valign="top" width="50%">
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The initial values of formal arguments specified in SystemVerilog as output are undetermined and implementation-dependent. See also Section 27.4.1.2. </div></td></tr><tr>
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<a href="00766.html" target="topic">E.5.4 Value changes for output and inout arguments</a> </div></td><td class="Element206" valign="top" width="50%">
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The SystemVerilog simulator is responsible for handling value changes for output and inout arguments. Such changes shall be detected and handled after the control returns from C code to SystemVerilog code. </div></td></tr><tr>
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<a href="00767.html" target="topic">E.5.5 context and non-context tasks and functions</a> </div></td><td class="Element206" valign="top" width="50%">
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Also refer to Section 27.4.3.<br><br>Some DPI imported tasks or functions or other interface functions called from them require that the context of their call be known. It takes special instrumentation of their call instances to provide such context; for example, a variable referring to the “current instance” might need to be set. To avoid any unnecessary overhead, imported tasks and function calls in SystemVerilog code are not instrumented unless the imported tasks or function is specified as context in its SystemVerilog import declaration.<br><br>All DPI export tasks and functions require that the context of their call is known. This... <a href="00767.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00768.html" target="topic">E.5.6 pure functions</a> </div></td><td class="Element206" valign="top" width="50%">
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See also Section 27.4.2.<br><br>Only non-void functions with no output or inout arguments can be specified as pure. Functions specified as pure in their corresponding SystemVerilog import declarations shall have no side effects; their results need to depend solely on the values of their input arguments. Calls to such functions can be removed by SystemVerilog compiler optimizations or replaced with the values previously computed for the same values of the input arguments.<br><br>Specifically, a pure function is assumed not to directly or indirectly (i.e., by calling other functions):<br>— perform any file operations<br>— read or write anything in the... <a href="00768.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00769.html" target="topic">E.5.7 Memory management</a> </div></td><td class="Element206" valign="top" width="50%">
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See also Section 27.4.1.4.<br><br>The memory spaces owned and allocated by C code and SystemVerilog code are disjoined. Each side is responsible for its own allocated memory. Specifically, C code shall not free the memory allocated by SystemVerilog code (or the SystemVerilog compiler) nor expect SystemVerilog code to free the memory allocated by C code (or the C compiler). This does not exclude scenarios in which C code allocates a block of memory, then passes a handle (i.e., a pointer) to that block to SystemVerilog code, which in turn calls a C function that directly (if it is the standard... <a href="00769.html" target="topic">more</a> </div></td></tr></table></div></div>
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