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<a href="#" onmousedown="showPopup(this, 'popup00447');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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第二十三章 系统任务与系统函数</div>
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主题 </div></td><td class="Element204" valign="top" width="50%">
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描述 </div></td></tr><tr>
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<a href="00267.html" target="topic">23.1 简介（一般信息）</a> </div></td><td class="Element206" valign="top" width="50%">
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SystemVerilog加入了几个将在下面几节中描述的系统任务和系统函数。<br><br>另外，SystemVerilog扩展了几个Verilog-2001系统任务的行为，这些扩展将在<a href="00272.html" target="topic">23.14节</a>中描述。 </div></td></tr><tr>
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<a href="00282.html" target="topic">23.2 确立时的typeof函数</a> </div></td><td class="Element206" valign="top" width="50%">
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<a href="00283.html" target="topic">23.3 typename函数</a> </div></td><td class="Element206" valign="top" width="50%">
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<a href="00284.html" target="topic">23.4 表达式尺寸系统函数</a> </div></td><td class="Element206" valign="top" width="50%">
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<a href="00285.html" target="topic">23.5 范围系统函数</a> </div></td><td class="Element206" valign="top" width="50%">
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<a href="00286.html" target="topic">23.6 Shortreal转换</a> </div></td><td class="Element206" valign="top" width="50%">
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Verilog 2001 defines a real data type, and the system functions $realtobits and $bitstoreal to permit exact bit pattern transfers between a real and a 64 bit vector. SystemVerilog adds the shortreal type, and in a parallel manner, $shortrealtobits and $bitstoshortreal are defined to permit exact bit transfers between a shortreal and a 32 bit vector. </div></td></tr><tr>
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<a href="00287.html" target="topic">23.7 数组查询系统函数</a> </div></td><td class="Element206" valign="top" width="50%">
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<a href="00288.html" target="topic">23.8 断言严重性系统任务</a> </div></td><td class="Element206" valign="top" width="50%">
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<a href="00289.html" target="topic">23.9 断言控制系统任务</a> </div></td><td class="Element206" valign="top" width="50%">
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<a href="00268.html" target="topic">23.10 断言系统函数</a> </div></td><td class="Element206" valign="top" width="50%">
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<a href="00269.html" target="topic">23.11 随机数系统函数</a> </div></td><td class="Element206" valign="top" width="50%">
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To supplement the Verilog $random system function, SystemVerilog provides three special system functions for generating pseudorandom numbers, $urandom, $urandom_range and $srandom. These system functions are presented in Section 12.12. </div></td></tr><tr>
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<a href="00270.html" target="topic">23.12 程序控制</a> </div></td><td class="Element206" valign="top" width="50%">
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In addition to the normal simulation control tasks ($stop and $finish), a program can use the $exit control task. When all programs exit, the simulation finishes and an implicit call to $finish is made. The usage of $exit is presented in Section 16.6 on program blocks. </div></td></tr><tr>
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<a href="00271.html" target="topic">23.13 覆盖系统函数</a> </div></td><td class="Element206" valign="top" width="50%">
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SystemVerilog has several built-in system functions for obtaining test coverage information: $coverage_control, $coverage_get_max, $coverage_get, $coverage_merge and $coverage_save. The coverage system functions are described in Section 29.2. </div></td></tr><tr>
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<a href="00272.html" target="topic">23.14 对Verilog-2001系统任务的增强</a> </div></td><td class="Element206" valign="top" width="50%">
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SystemVerilog adds system tasks and system functions as described in the following sections. In addition, SystemVerilog extends the behavior of the following:
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<li class="Element607">%u and %z format specifiers:
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<li class="Element608">For packed data, %u and %z are defined to operate as though the operation were applied to the equivalent vector.</li>
<li class="Element608">For unpacked struct data, %u and %z are defined to apply as though the operation were performed on each member in declaration order.</li>
<li class="Element608">For unpacked union data, %u and %z are defined to apply as though the operation were performed on the first member in declaration order.</li>
<li class="Element608">%u and %z are not defined... <a href="00272.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00273.html" target="topic">23.15 $readmemb与$readmemh</a> </div></td><td class="Element206" valign="top" width="50%">
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<a href="00276.html" target="topic">23.16 $writememb and $writememh</a> </div></td><td class="Element206" valign="top" width="50%">
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SystemVerilog introduces system tasks $writememb and $writememh: </div></td></tr><tr>
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<a href="00280.html" target="topic">23.17 File format considerations for multi-dimensional unpacked arrays</a> </div></td><td class="Element206" valign="top" width="50%">
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In SystemVerilog, $readmemb, $readmemh, $writememb and $writememh can work with multi-dimensional unpacked arrays.<br><br>The file contents are organized in row-major order, with each dimension’s entries ranging from low to high address. This is backward compatible with plain Verilog memories.<br><br>In this organization, the lowest dimension (i.e. the right-most dimension in the array declaration) varies the most rapidly. There is a hierarchical sense to the file data. The higher dimensions contain words of lowerdimension data, sorted in row-major order. Each successive lower dimension is entirely enclosed as part of higher dimension words.<br><br>As an example of file format organization, here is... <a href="00280.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00281.html" target="topic">23.18 System task arguments for multi-dimensional unpacked arrays</a> </div></td><td class="Element206" valign="top" width="50%">
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The $readmemb, $readmemh, $writememb, and $writememh signatures are shown below: </div></td></tr></table></div></div>
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