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📁 这是一本关于verilog编程语言的教程,对学习verilog语言有帮助
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<title>5.7 信号别名</title>
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<a href="00875.html" target="topic">第五章 数据声明</a></div>
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<a href="#" onmousedown="showPopup(this, 'popup00109');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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5.7 信号别名</div>
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Verilog <span style="color: #0000FF">assign</span>语句是单向赋值并可以结合一个延时和强度变化。为了建模一个双向短路连接，很有必要使用<span style="color: #0000FF">alias</span>语句。一个别名列表的成员是那些共享相同物理网络的信号。下面的例子实现了总线<i>A</i>和总线<i>B</i>之间的字节顺序交换。 </p><div class="Element170">
<a href="#" onclick="CopyElementToClipboard('code00196');">Copy Code</a></div>
<div class="Element13"><div class="Element12" id="code00196"><pre class="Element12"><span style="color: #0000FF">module</span> byte_swap <span style="color: #800080">(</span><span style="color: #0000FF">inout wire</span> <span style="color: #800080">[</span><span style="color: #FF0000">31</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> A<span style="color: #800080">,</span> <span style="color: #0000FF">inout wire</span> <span style="color: #800080">[</span><span style="color: #FF0000">31</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> B<span style="color: #800080">);</span>
    <span style="color: #0000FF">alias</span> <span style="color: #800080">{</span>A<span style="color: #800080">[</span><span style="color: #FF0000">7</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">],</span>AA<span style="color: #800080">[</span><span style="color: #FF0000">15</span><span style="color: #800080">:</span><span style="color: #FF0000">8</span><span style="color: #800080">],</span>AA<span style="color: #800080">[</span><span style="color: #FF0000">23</span><span style="color: #800080">:</span><span style="color: #FF0000">16</span><span style="color: #800080">],</span>AA<span style="color: #800080">[</span><span style="color: #FF0000">31</span><span style="color: #800080">:</span><span style="color: #FF0000">24</span><span style="color: #800080">]} = </span>B<span style="color: #800080">;</span>
<span style="color: #0000FF">endmodule</span></pre></div></div>
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下面的例子从一个四字节总线中剥离最低和最高有效字节： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00197"><pre class="Element12"><span style="color: #0000FF">module</span> byte_rip <span style="color: #800080">(</span><span style="color: #0000FF">inout wire</span> <span style="color: #800080">[</span><span style="color: #FF0000">31</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> W<span style="color: #800080">,</span> <span style="color: #0000FF">inout wire</span> <span style="color: #800080">[</span><span style="color: #FF0000">7</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> LSB<span style="color: #800080">,</span> MSB<span style="color: #800080">);</span>
<span style="color: #0000FF">    alias</span> W<span style="color: #800080">[</span><span style="color: #FF0000">7</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> <span style="color: #800080">=</span> LSB<span style="color: #800080">;</span>
<span style="color: #0000FF">    alias</span> W<span style="color: #800080">[</span><span style="color: #FF0000">31</span><span style="color: #800080">:</span><span style="color: #FF0000">24</span><span style="color: #800080">]</span> <span style="color: #800080">=</span> MSB<span style="color: #800080">;</span>
<span style="color: #0000FF">endmodule</span></pre></div></div>
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位覆盖规则与具有相同成员类型的压缩联合体的位覆盖规则相同：每一个成员应具有相同的尺寸，并且连通性独立于仿真主机。使用别名语句连接的线网必须是类型兼容的。换句话说，它们必须是相同的线网类型。例如，使用<span style="color: #0000FF">alias</span>语句将一个<span style="color: #0000FF">wand</span>线网连接到<span style="color: #0000FF">wor</span>线网是非法的。这比应用到在端口上结合的线网具有更严格的规则，因为别名的作用范围是受限的并且这样的连接很可能是一个设计错误。变量和层次化引用不能使用在别名语句中。如果违背这些规则，那么会认为是一个严重错误。&nbsp;</p>
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&nbsp;</p>
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相同的线网可以出现在多条别名语句中。效果是累积的。下面两个例子是等价的。在这两种情况下，<i>low12[11:4]</i>和<i>high12[7:0]</i>共享相同的线网。 </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00198"><pre class="Element12"><span style="color: #0000FF">module</span> overlap<span style="color: #800080">(</span><span style="color: #0000FF">inout wire</span> <span style="color: #800080">[</span><span style="color: #FF0000">15</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> bus16<span style="color: #800080">,</span> <span style="color: #0000FF">inout wire</span> <span style="color: #800080">[</span><span style="color: #FF0000">11</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> low12<span style="color: #800080">,</span> high12<span style="color: #800080">);</span>
<span style="color: #0000FF">    alias</span> bus16<span style="color: #800080">[</span><span style="color: #FF0000">11</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> <span style="color: #800080">=</span> low12<span style="color: #800080">;</span>
<span style="color: #0000FF">    alias</span> bus16<span style="color: #800080">[</span><span style="color: #FF0000">15</span><span style="color: #800080">:</span><span style="color: #FF0000">4</span><span style="color: #800080">]</span> <span style="color: #800080">=</span> high12<span style="color: #800080">;</span>
<span style="color: #0000FF">endmodule</span>

<span style="color: #0000FF">module</span> overlap<span style="color: #800080">(</span><span style="color: #0000FF">inout wire</span> <span style="color: #800080">[</span><span style="color: #FF0000">15</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> bus16<span style="color: #800080">,</span> <span style="color: #0000FF">inout wire</span> <span style="color: #800080">[</span><span style="color: #FF0000">11</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> low12<span style="color: #800080">,</span> high12<span style="color: #800080">);</span>
<span style="color: #0000FF">    alias</span> bus16 <span style="color: #800080">= {</span>high12<span style="color: #800080">,</span> low12<span style="color: #800080">[</span><span style="color: #FF0000">3</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]};</span>
<span style="color: #0000FF">    alias</span> high12<span style="color: #800080">[</span><span style="color: #FF0000">7</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> <span style="color: #800080">=</span> low12<span style="color: #800080">[</span><span style="color: #FF0000">11</span><span style="color: #800080">:</span><span style="color: #FF0000">4</span><span style="color: #800080">];</span>
<span style="color: #0000FF">endmodule</span></pre></div></div>
<p class="Element10">
为了在规范中避免错误，SystemVerilog不允许从一个单独的变量中为它本身指定别名，也不允许多次指定一个特定的别名。上面代码的下面版本是非法的，因为高四位与低四位在两条语句中是相同的： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00199"><pre class="Element12"><span style="color: #0000FF">alias</span> bus16 <span style="color: #800080">= {</span>high12<span style="color: #800080">[</span><span style="color: #FF0000">11</span><span style="color: #800080">:</span><span style="color: #FF0000">8</span><span style="color: #800080">],</span> low12<span style="color: #800080">};</span>
<span style="color: #0000FF">alias</span> bus16 <span style="color: #800080">= {</span>high12<span style="color: #800080">,</span> low12<span style="color: #800080">[</span><span style="color: #FF0000">3</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]};</span></pre></div></div>
<p class="Element10">
下面的语句也是非法的，因为<i>bus16</i>的各位是它本身的别名： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00200"><pre class="Element12"><span style="color: #0000FF">alias</span> bus16 <span style="color: #800080">= {</span>high12<span style="color: #800080">,</span> bus16<span style="color: #800080">[</span><span style="color: #FF0000">3</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]} = {</span>bus16<span style="color: #800080">[</span><span style="color: #FF0000">15</span><span style="color: #800080">:</span><span style="color: #FF0000">12</span><span style="color: #800080">],</span> low12<span style="color: #800080">};</span></pre></div></div>
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