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<a href="#" onmousedown="showPopup(this, 'popup00365');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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17.13.4 在过程化代码外部使用并发断言语句</div>
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A concurrent assertion statement can be used outside of a procedural context. It can be used within a module, an interface, or a program. A concurrent assertion statement is an assert, an assume, or a cover statement.Such a concurrent assertion statement uses the always semantics. </p>
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The following two forms are equivalent: </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00752"><pre class="Element12">assert property ( property_spec ) action_block
always assert property ( property_spec ) action_block ;</pre></div></div>
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Similarly, the following two forms are equivalent: </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00753"><pre class="Element12">cover property ( property_spec ) statement_or_null
always cover property ( property_spec ) statement_or_null</pre></div></div>
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For example: </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00754"><pre class="Element12">module top(input bit clk);
logic a,b,c;
property rule3;
@(posedge clk) a |-> b ##1 c;
endproperty
a1: assert property (rule3);
...
endmodule</pre></div></div>
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rule3 is a property declared in module top. The assert statement a1 starts checking the property from the beginning to the end of simulation. The property is always checked. Similarly, </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00755"><pre class="Element12">module top(input bit clk);
logic a,b,c;
sequence seq3;
@(posedge clk) b ##1 c;
endsequence
c1: cover property (seq3);
...
endmodule</pre></div></div>
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The cover statement c1 starts coverage of the sequence seq3 from beginning to the end of simulation. The sequence is always monitored for coverage.</p></div>
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