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<a href="#" onmousedown="showPopup(this, 'popup00422');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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20.1 简介（一般信息）</div>
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Functional verification comprises a large portion of the resources required to design and validate a complex system. Often, the validation must be comprehensive without redundant effort. To minimize wasted effort, coverage is used as a guide for directing verification resources by identifying tested and untested portions of the design. </p>
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Coverage is defined as the percentage of verification objectives that have been met. It is used as a metric for evaluating the progress of a verification project in order to reduce the number of simulation cycles spent in verifying a design Broadly speaking, there are two types of coverage metrics. Those that can be automatically extracted from the design code, such as code coverage, and those that are user-specified in order to tie the verification environment to the design intent or functionality. This latter form is referred to as Functional Coverage, and is the topic of this section. </p>
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Functional coverage is a user-defined metric that measures how much of the design specification, as enumerated by features in the test plan, has been exercised. It can be used to measure whether interesting scenarios, corner cases, specification invariants, or other applicable design conditions—captured as features of the test plan—have been observed, validated and tested. </p>
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The key aspects of functional coverage are:
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<li class="Element606">It is user-specified, and is not automatically inferred from the design</li>
<li class="Element606">It is based on the design specification (i.e., its intent) and is thus independent of the actual design code or its structure.</li>
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Since it is fully specified by the user, functional coverage requires more up front effort (someone has to write the coverage model). Functional coverage also requires a more structured approach to verification. Although functional coverage can shorten the overall verification effort and yield higher quality designs, these shortcomings can impede its adoption. </p>
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The SystemVerilog functional coverage extensions address these shortcomings by providing language constructs for easy specification of functional coverage models. This specification can be efficiently executed by the SystemVerilog simulation engine, thus, enabling coverage data manipulation and analysis tools that speed up the development of high quality tests. The improved set of tests can exercise more corner cases and required scenarios, without redundant work. </p>
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The SystemVerilog functional coverage constructs enable:
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<li class="Element606">Coverage of variables and expressions, as well as cross coverage between them.</li>
<li class="Element606">Automatic as well as user-defined coverage bins.</li>
<li class="Element606">Associate bins with sets of values, transitions, or cross products.</li>
<li class="Element606">Filtering conditions at multiple levels.</li>
<li class="Element606">Events and sequences to automatically trigger coverage sampling.</li>
<li class="Element606">Procedural activation and query of coverage.</li>
<li class="Element606">Optional directives to control and regulate coverage.</li>
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