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18.8 端口声明</div>
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<div class="Element13"><div class="Element12" id="code00810"><pre class="Element12">inout_declaration ::= <span style="color: #008000">// 引用自附录A.2.1.2</span>
<strong><span style="color: #FF0000">inout</span></strong> port_type list_of_port_identifiers
input_declaration ::=
<strong><span style="color: #FF0000">input</span></strong> port_type list_of_port_identifiers
| <strong><span style="color: #FF0000">input</span></strong> data_type list_of_variable_identifiers
output_declaration ::=
<strong><span style="color: #FF0000">output</span></strong> port_type list_of_port_identifiers
| <strong><span style="color: #FF0000">output</span></strong> data_type list_of_variable_port_identifiers
interface_port_declaration ::=
interface_identifier list_of_interface_identifiers
| interface_identifier<strong><span style="color: #FF0000">.</span></strong>modport_identifier list_of_interface_identifiers
ref_declaration ::= <strong><span style="color: #FF0000">ref</span></strong> data_type list_of_port_identifiers
port_type ::= <span style="color: #008000">// 引用自附录A.2.2.1</span>
[net_type_or_trireg] [signing] {packed_dimension}</pre></div></div>
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<strong>语法18-4 — 端口声明语法（摘录自附录A）</strong></p><p class="Element10">
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With SystemVerilog, a port can be a declaration of a net, an interface, an event, or a variable of any type, including an array, a structure or a union. </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00811"><pre class="Element12">typedef struct {
bit isfloat;
union { int i; shortreal f; } n;
} tagged_st; // named structure
module mh1 (input int in1, input shortreal in2, output tagged_st out);
...
endmodule</pre></div></div>
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For the first port, if neither a type nor a direction is specified, then it shall be assumed to be a member of a port list, and any port direction or type declarations must be declared after the port list. This is compatible with the Verilog-1995 syntax. If the first port type but no direction is specified, then the port direction shall default to inout. If the first port direction but no type is specified, then the port type shall default to wire. This default type can be changed using the ‘default_nettype compiler directive, as in Verilog. </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00812"><pre class="Element12">// Any declarations must follow the port list, because first port does not
// have either a direction or type specified; Port directions default to inout
module mh4(x, y);
wire x;
tri0 y;
...
endmodule</pre></div></div>
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For subsequent ports in the port list, if the type and direction are omitted, then both are inherited from the previous port. If only the direction is omitted, then it is inherited from the previous port. If only the type is omitted, it shall default to wire. This default type can be changed using the ‘default_nettype compiler directive, as in Verilog. </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00813"><pre class="Element12">// second port inherits its direction and type from previous port
module mh3 (input byte a, b);
...
endmodule</pre></div></div>
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Generic interface ports cannot be declared using the Verilog-1995 list of ports style. Generic interface ports can only be declared by using a list of port declaration style. </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00814"><pre class="Element12">module cpuMod(interface d, interface j);
...
endmodule</pre></div></div>
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