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E.6.7 Canonical representation of packed arrays</div>
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The Direct Programming Interface defines the canonical representation of packed 2-state (type svBitVec32) and 4-state arrays (type svLogicVec32). This canonical representation is derived from on the Verilog legacy PLI’s avalue/bvalue representation of 4-state vectors. Library functions provide the translation between the representation used in a simulator and the canonical representation of packed arrays. </p>
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A packed array is represented as an array of one or more elements (of type svBitVec32 for 2-state values and svLogicVec32 for 4-state values), each element representing a group of 32 bits.The first element of an array contains the 32 least-significant bits, next element contains the 32 more-significant bits, and so on. The last element can contain a number of unused bits. The contents of these unused bits is undetermined and the user is responsible for the masking or the sign extension (depending on the sign) for the unused bits. </p>
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Table E-2 defines the encoding used for a packed logic array represented as svLogicVec32. </p><p class="Element10" style="text-align: center">
<strong>Table E-2: Encoding of bits in svLogicVec32</strong> </p>
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