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18.9 端口表达式列表</div>
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Verilog 1364-2001 created a list_of_port_declarations alternate style which minimized the duplication of data used to specify the ports of a module. SystemVerilog adds an explicitly named port declaration to that style, allowing elements of arrays and structures, concatenations of elements, or aggregate expressions of elements declared in a module, interface or program to be specified on the port list. </p>
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Like explicitly named ports in a module port declaration, port identifiers exist in their own namespace for each port list. When port item is just a simple port identifier, that identifier is used as both a reference to an interface item and a port identifier. Once a port identifier has been defined, there shall not be another port definition with this same name. </p>
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<div class="Element13"><div class="Element12" id="code00815"><pre class="Element12">module mymod (
output .P1(r[3:0]),
output .P2(r[7:4]),
ref .Y(x),
input bit R );
logic [7:0] r;
int x;
...
endmodule</pre></div></div>
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The self-determined type of the port expression becomes the type for the port. If the port expression is to be an aggregate expression, then a cast must be used since self-determined aggregate expressions are not allowed. The port expression must resolve to a legal expression for type of module port (See section 18.12—Port connection rules). The port expression is optional because ports can be defined that do not connect to anything internal to the port.</p></div>
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