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SystemVerilog 3.1a语言参考手册</div>
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第二十四章 VCD数据</div>
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SystemVerilog并没有扩展VCD格式。某些SystemVerilog数据类型能够通过伪装成一个Verilog数据类型被转储到一个标准的VCD文件。下面的表格列出了基本的SystemVerilog数据类型以及在VCD转储中与Verilog数据类型的映射。 </p>
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<strong>表格24-1：VCD类型映射</strong> </p><div class="Element63">
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SystemVerilog </div></td><td class="Element65" valign="top" width="29%">
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Verilog </div></td><td class="Element65" valign="top" width="38%">
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Size </div></td></tr><tr>
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bit </div></td><td class="Element67" valign="top" width="29%">
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reg </div></td><td class="Element67" valign="top" width="38%">
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Size of packed dimension </div></td></tr><tr>
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logic </div></td><td class="Element67" valign="top" width="29%">
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reg </div></td><td class="Element67" valign="top" width="38%">
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Size of packed dimension </div></td></tr><tr>
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int </div></td><td class="Element67" valign="top" width="29%">
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integer </div></td><td class="Element67" valign="top" width="38%">
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32 </div></td></tr><tr>
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shortint </div></td><td class="Element67" valign="top" width="29%">
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integer </div></td><td class="Element67" valign="top" width="38%">
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16 </div></td></tr><tr>
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longint </div></td><td class="Element67" valign="top" width="29%">
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integer </div></td><td class="Element67" valign="top" width="38%">
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64 </div></td></tr><tr>
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shortreal </div></td><td class="Element67" valign="top" width="29%">
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real </div></td><td class="Element67" valign="top" width="38%">
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byte </div></td><td class="Element67" valign="top" width="29%">
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reg </div></td><td class="Element67" valign="top" width="38%">
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8 </div></td></tr><tr>
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enum </div></td><td class="Element67" valign="top" width="29%">
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integer </div></td><td class="Element67" valign="top" width="38%">
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32 </div></td></tr></table></div></div>
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Packed arrays and structures are dumped as a single vector of reg. Multiple packed array dimensions are collapsed into a single dimension. </p>
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If an enum declaration specified a type, it is dumped as that type rather than the default shown above. </p>
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Unpacked structures appear as named fork...join blocks, and their member elements of the structure appear as the types above. Since named fork...join blocks with variable declarations are seldom used in testbenches and hardware models, this makes structures easy to distinguish from variables declared in begin...end blocks, which are more frequently used in testbenches and models. </p>
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As in Verilog 2001, unpacked arrays and automatic variables are not dumped. </p>
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Note that the current VCD format does not indicate whether a variable has been declared as signed or unsigned.</p></div>
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