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18.12 端口连接规则</div>
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通过允许所有变量数据类型都能够通过端口传递，SystemVerilog扩展了Verilog的端口连接能力。通过允许端口连接的两侧具有相同的兼容类型，并且通过允许对变量的连续赋值，SystemVerilog做到了这一点。SystemVerilog还产生了一个新的端口限定符类型，<span style="color: #0000FF">ref</span>，它允许共享的变量通过传递一个层次化的引用来跨越一个端口。</p></div>
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描述 </div></td></tr><tr>
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<a href="00196.html" target="topic">18.12.1 变量的端口连接规则</a> </div></td><td class="Element206" valign="top" width="50%">
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如果一个端口声明具有一个变量数据类型，那么它的方向控制端口实例如何连接，变量的端口连接规则如下：
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<li class="Element604">一个输入端口可以连接到一个兼容类型的任意表达式。A continuous assignment shall be implied when a variable is connected to an input port declaration. Assignments to variables declared as an input port shall be illegal. If left unconnected, the port shall have the default initial value corresponding to the data type.</li>
<li class="Element604">An output port can be connected to a variable (or a concatenation) of a compatible data type. A continuous assignment shall be implied when a variable is connected the output port of an instance. Procedural or continuous assignments to a variable connected to the output port of an instance shall be illegal.</li>
<li class="Element604">An output port can... <a href="00196.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00197.html" target="topic">18.12.2 线网的端口连接规则</a> </div></td><td class="Element206" valign="top" width="50%">
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If a port declaration has a wire type (which is the default), or any other net type, then its direction controls how it can be connected as follows:
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<li class="Element605">An input can be connected to any expression of a compatible data type. If left unconnected, it shall have the value 'z.</li>
<li class="Element605">An output can be connected to a net type (or a concatenation of net types) or a compatible variable type (or a concatenation of variable types).</li>
<li class="Element605">An inout can be connected to a net type (or a concatenation of net types) or left unconnected, but not to a variable type.... <a href="00197.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00198.html" target="topic">18.12.3 接口的端口连接规则</a> </div></td><td class="Element206" valign="top" width="50%">
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A port declaration can be a generic interface or named interface type. An interface port instance must always be connected to an interface instance or a higher-level interface port. An interface port cannot be left unconnected.<br><br>If a port declaration has a generic interface type, then it can be connected to an interface instance of any type. If a port declaration has a named interface type, then it must be connected to an interface instance of the identical type. </div></td></tr><tr>
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<a href="00199.html" target="topic">18.12.4 兼容的端口类型</a> </div></td><td class="Element206" valign="top" width="50%">
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The same rules for assignment compatibility are used for compatible port types for ports declared as an input or an output variable, or for output ports connected to variables. SystemVerilog does not change any of the other port connection compatibility rules </div></td></tr><tr>
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<a href="00200.html" target="topic">18.12.5 非压缩数组端口与实例数组</a> </div></td><td class="Element206" valign="top" width="50%">
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For an unpacked array port, the port and the array connected to the port must have the same number of unpacked dimensions, and each dimension of the port must have the same size as the corresponding dimension of the array being connected.<br><br>If the size and type of the port connection match the size and type of a single instance port, the connection shall be made to each instance in an array of instances.<br><br>If the port connection is an unpacked array, the unpacked array dimensions of each port connection shall be compared with the dimensions of the instance array.... <a href="00200.html" target="topic">more</a> </div></td></tr></table></div></div>
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