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<a href="00871.html" target="topic">第十五章 时钟控制块</a></div>
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<a href="#" onmousedown="showPopup(this, 'popup00309');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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15.10 周期延时：##</div>
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<span style="color: #800080">##</span>操作符可以被用来将执行延时一个指定数目的时钟控制事件，或者时钟周期。 </p>
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周期延时语句的语法如下： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00544"><pre class="Element12">procedural_timing_control_statement ::= <span style="color: #008000">// 引用自附录A.6.5</span>
procedural_timing_control statement_or_null
procedural_timing_control ::=
...
| cycle_delay
cycle_delay ::= <span style="color: #008000">// 引用自附录A.6.11</span>
<strong><span style="color: #FF0000">##</span></strong> integral_number
| <strong><span style="color: #FF0000">##</span></strong> identifier
| <strong><span style="color: #FF0000">##</span></strong> <strong><span style="color: #FF0000">(</span></strong>expression<strong><span style="color: #FF0000">)</span></strong></pre></div></div>
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<strong>语法15-2 — 周期延时语法（摘录自附录A）</strong></p><p class="Element10">
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<span class="Element146">expression</span>可以是任何能够计算成一个正的整数值的SystemVerilog表达式。 </p>
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由什么组成一个周期是通过有效的缺省时钟控制确定的（参见<a href="00121.html" target="topic">15.11节</a>）。如果当前的模块、接口或程序没有指定缺省的时钟控制的话，编译器应该发布一条错误。 </p>
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例子： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00545"><pre class="Element12"><span style="color: #800080">##</span> 5<span style="color: #800080">;</span> <span style="color: #008000">// 使用缺省时钟控制等待5个周期（时钟控制事件）</span>
<span style="color: #800080">##</span> <span style="color: #800080">(</span>j<span style="color: #800080">+</span><span style="color: #FF0000">1</span><span style="color: #800080">);</span> <span style="color: #008000">// 使用缺省时钟控制等待j+1个周期（时钟控制事件）</span></pre></div></div>
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