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<a href="00867.html" target="topic">第十六章 程序块</a></div>
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<a href="#" onmousedown="showPopup(this, 'popup00318');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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16.2 程序结构</div>
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一个典型的程序包含类型和数据声明、子例程、设计的连接、以及一个或多个过程化的代码流。设计和测试平台间的连接使用与SystemVerilog说明端口连接（包括接口）相同的互连机制。程序块的语法如下： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00560"><pre class="Element12">program_nonansi_header ::= <span style="color: #008000">// 引用自附录A.1.3</span>
{attribute_instance} <strong><span style="color: #FF0000">program</span></strong> [lifetime] program_identifier
[parameter_port_list] list_of_ports<strong><span style="color: #FF0000">;</span></strong>
program_ansi_header ::=
{attribute_instance} <strong><span style="color: #FF0000">program</span></strong> [lifetime] program_identifier
[parameter_port_list] [list_of_port_declarations]<strong><span style="color: #FF0000">;</span></strong>
program_declaration ::=
program_nonansi_header [timeunits_declaration] {program_item}
<strong><span style="color: #FF0000">endprogram</span></strong> [<strong><span style="color: #FF0000">:</span></strong> program_identifier]
| program_ansi_header [timeunits_declaration] {non_port_program_item}
<strong><span style="color: #FF0000">endprogram</span></strong> [<strong><span style="color: #FF0000">:</span></strong> program_identifier]
| {attribute_instance} program program_identifier<strong><span style="color: #FF0000">(.*);</span></strong>
[timeunits_declaration] {program_item}
<strong><span style="color: #FF0000">endprogram</span></strong> [<strong><span style="color: #FF0000">:</span></strong> program_identifier]
| <strong><span style="color: #FF0000">extern</span></strong> program_nonansi_header
| <strong><span style="color: #FF0000">extern</span></strong> program_ansi_header
program_item ::= <span style="color: #008000">// 引用自附录A.1.7</span>
port_declaration<strong><span style="color: #FF0000">;</span></strong>
| non_port_program_item
non_port_program_item ::=
{attribute_instance} continuous_assign
| {attribute_instance} module_or_generate_item_declaration
| {attribute_instance} specparam_declaration
| {attribute_instance} initial_construct
| {attribute_instance} concurrent_assertion_item
| {attribute_instance} timeunits_declaration18
lifetime ::= <strong><span style="color: #FF0000">static</span></strong> | <strong><span style="color: #FF0000">automatic </span><span style="color: #008000"></strong>// 引用自附录A.2.1.3</span></pre></div></div>
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<strong>语法16-1 — 程序声明语法（摘录自附录A）</strong></p><p class="Element10">
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例如： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00561"><pre class="Element12"><span style="color: #0000FF">program</span> test <span style="color: #800080">(</span><span style="color: #0000FF">input</span> clk<span style="color: #800080">,</span> <span style="color: #0000FF">input</span> <span style="color: #800080">[</span><span style="color: #FF0000">16</span><span style="color: #800080">:</span><span style="color: #FF0000">1</span><span style="color: #800080">]</span> addr<span style="color: #800080">,</span> <span style="color: #0000FF">inout</span> <span style="color: #800080">[</span><span style="color: #FF0000">7</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> data<span style="color: #800080">);</span>
<span style="color: #0000FF">initial</span> ...
<span style="color: #0000FF">endprogram</span></pre></div></div>
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</p>
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或者 </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00562"><pre class="Element12"><span style="color: #0000FF">program</span> test <span style="color: #800080">(</span><span style="color: #0000FF">interface</span> device_ifc<span style="color: #800080">);</span>
<span style="color: #0000FF">initial</span> ...
<span style="color: #0000FF">endprogram</span></pre></div></div>
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</p>
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一个更完整的例子包含在<a href="00132.html" target="topic">15.7节</a>和<a href="00133.html" target="topic">15.8节</a>中。 </p>
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尽管程序结构是SystemVerilog的新结构，然而包含程序却是一个自然的扩展。程序结构可以被看作是一个具有特殊执行语义的叶子模块。一旦被声明，一个程序块可以在需要的层次位置（典型情况位于顶层）中被实例化，并且它的端口可以以任意其它模块相同的方式被连接。 </p>
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程序块可以在模块或接口内部嵌套。这就使得多个协同操作的程序能够共享作用范围内的本地变量。没有端口的嵌套程序或者没有被显式实例化的顶层程序被隐含地实例化一次。被隐含地实例化的程序具有相同的实例和声明名字。例如： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00563"><pre class="Element12"><span style="color: #0000FF">module</span> test<span style="color: #800080">(</span>...<span style="color: #800080">)</span>
<span style="color: #0000FF">int</span> shared<span style="color: #800080">;</span> <span style="color: #008000">// 被程序p1和p2共享的变量</span>
<span style="color: #0000FF">program</span> p1<span style="color: #800080">;</span>
...
<span style="color: #0000FF">endprogram</span>
<span style="color: #0000FF">program</span> p2<span style="color: #800080">;</span>
...
<span style="color: #0000FF">endprogram</span> <span style="color: #008000">// 在模块test中，p1和p2被隐含地实例化一次</span>
<span style="color: #0000FF">endmodule</span></pre></div></div>
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</p>
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一个程序块可以包含一个或多个<span style="color: #0000FF">initial</span>块，但不能包含<span style="color: #0000FF">always</span>块、<span style="color: #0000FF">UDP</span>、模块、接口或其它程序。 </p>
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程序内的类型和数据声明对于程序作用范围来讲是本地的并具有静态的生命周期。非程序变量只能使用无阻塞赋值进行赋值。对程序变量使用无阻塞赋值或对设计变量（非程序变量）使用阻塞赋值都应该是一个错误。从程序块外部引用程序变量也是错误的。</p></div>
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