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<a href="#" onmousedown="showPopup(this, 'popup00542');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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29.3.1 Specifying the signal that holds the current state</div>
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Use the following pragma to identify the vector signal that holds the current state of the FSM: </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code01003"><pre class="Element12">/* tool state_vector signal_name */</pre></div></div>
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where tool and state_vector are required keywords. This pragma needs to be specified inside the module definition where the signal is declared. </p>
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Another pragma is also required, to specify an enumeration name for the FSM. This enumeration name is also specified for the next state and any possible states, associating them with each other as part of the same FSM. </p>
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There are two ways to do this:
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<li class="Element600">Use the same pragma:</li>
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<div class="Element13"><div class="Element12" id="code01004"><pre class="Element12">/* tool state_vector signal_name enum enumeration_name */</pre></div></div>
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<li class="Element600">Use a separate pragma in the signal’s declaration:</li>
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<div class="Element13"><div class="Element12" id="code01005"><pre class="Element12">/* tool state_vector signal_name */
reg [7:0] /* tool enum enumeration_name */ signal_name;</pre></div></div>
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In either case, enum is a required keyword; if using a separate pragma, tool is also a required keyword and the pragma needs to be specified immediately after the bit-range of the signal.</p></div>
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