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29.2.1 Predefined coverage constants in SystemVerilog</div>
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The following predefined ‘defines represent basic real-time coverage capabilities accessible directly from SystemVerilog. </p>
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— Coverage control </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00990"><pre class="Element12">‘define SV_COV_START 0
‘define SV_COV_STOP 1
‘define SV_COV_RESET 2
‘define SV_COV_CHECK 3</pre></div></div>
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— Scope definition (hierarchy traversal/accumulation type) </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00991"><pre class="Element12">‘define SV_COV_MODULE 10
‘define SV_COV_HIER 11</pre></div></div>
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— Coverage type identification </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00992"><pre class="Element12">‘define SV_COV_ASSERTION 20
‘define SV_COV_FSM_STATE 21
‘define SV_COV_STATEMENT 22
‘define SV_COV_TOGGLE 23</pre></div></div>
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— Status results </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00993"><pre class="Element12">‘define SV_COV_OVERFLOW -2
‘define SV_COV_ERROR -1
‘define SV_COV_NOCOV 0
‘define SV_COV_OK 1
‘define SV_COV_PARTIAL 2</pre></div></div>
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