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<a href="00883.html" target="topic">附录E DPI C-layer</a>, <a href="01035.html" target="topic">主题</a></div>
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<a href="#" onmousedown="showPopup(this, 'popup00779');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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E.6 Data types</div>
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This section defines the data types of the C-layer of the Direct Programming Interface.</p></div>
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<a href="00771.html" target="topic">E.6.1 Limitations</a> </div></td><td class="Element206" valign="top" width="50%">
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Packed arrays can have an arbitrary number of dimensions; though they are eventually always equivalent to a one-dimensional packed array and treated as such. If the packed part of an array in the type of a formal argument in SystemVerilog is specified as multi-dimensional, the SystemVerilog compiler linearizes it. Although the original ranges are generally preserved for open arrays, if the actual argument has a multidimensional packed part of the array, it shall be normalized into an equivalent one-dimensional packed array.<br><br>NOTE—The actual argument can have both packed and unpacked parts of an array; either can be multidimensional. </div></td></tr><tr>
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<a href="00772.html" target="topic">E.6.2 Duality of types: SystemVerilog types vs. C types</a> </div></td><td class="Element206" valign="top" width="50%">
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A value that crosses the Direct Programming Interface is specified in SystemVerilog code as a value of SystemVerilog type, while the same value shall be specified in C code as a value of C type. Therefore, each data type that is passed through the Direct Programming Interface requires two matching type definitions: the SystemVerilog definition and C definition.<br><br>The user needs to provide such matching definitions. Specifically, for each SystemVerilog type used in the import declarations or export declarations in SystemVerilog code, the user shall provide the equivalent type definition in C reflecting the argument passing mode for the particular... <a href="00772.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00773.html" target="topic">E.6.3 Data representation</a> </div></td><td class="Element206" valign="top" width="50%">
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DPI imposes the following additional restrictions on the representation of SystemVerilog data types.
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<li class="Element600">SystemVerilog types that are not packed and that do not contained packed elements have C compatible representation.</li>
<li class="Element600">Basic integer and real data types are represented as defined in Annex E.6.4.</li>
<li class="Element600">Enumeration types are represented as the types associated with them. Enumerated names are not available on C side of interface.</li>
<li class="Element600">Representation of packed types is implementation-dependent.</li>
<li class="Element600">Unpacked arrays embedded in a structure have C compatible layout regardless of the type of elements. Similarly, standalone arrays passed as actuals to a sized formal argument have C compatible representation.... <a href="00773.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00774.html" target="topic">E.6.4 Basic types</a> </div></td><td class="Element206" valign="top" width="50%">
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Table E-1 defines the mapping between the basic SystemVerilog data types and the corresponding C types. </p><p class="Element207" style="text-align: center">
<strong>Table E-1: Mapping data types</strong><br><img src="table_e_1.png" border="0" alt="" title=""><br> </p><p class="Element207">
?Encodings for bit and logic are given in file svdpi.h. Refer to Annex E.9.1.1.<br><br>The DPI interface also supports the SystemVerilog and C unsigned integer data types that correspond to the mappings Table E-1 shows for their signed equivalents.<br><br>Note that input mode arguments of type byte unsigned and shortint unsigned are not equivalent to bit[7:0] or bit[15:0], respectively, since the former are passed as C types unsigned char and unsigned short and the latter are passed as C... <a href="00774.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00775.html" target="topic">E.6.5 Normalized ranges</a> </div></td><td class="Element206" valign="top" width="50%">
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Packed arrays are treated as one-dimensional; the unpacked part of an array can have an arbitrary number of dimensions. Normalized ranges mean [n-1:0] indexing for the packed part and [0:n-1] indexing for a dimension of the unpacked part of an array. Normalized ranges are used for accessing all arguments but open arrays. The canonical representation of packed arrays also uses normalized ranges. </div></td></tr><tr>
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<a href="00776.html" target="topic">E.6.6 Mapping between SystemVerilog ranges and normalized ranges</a> </div></td><td class="Element206" valign="top" width="50%">
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The SystemVerilog ranges for a formal argument specified as an open array are those of the actual argument for a particular call. Open arrays are accessible, however, by using their original ranges and the same indexing as in the SystemVerilog code.<br><br>For all other types of arguments, i.e., all arguments but open arrays, the SystemVerilog ranges are defined in the corresponding SystemVerilog import or export declaration. Normalized ranges are used for accessing such arguments in C code. The mapping between SystemVerilog ranges and normalized ranges is defined as follows.
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<li value="1" class="Element600">If a packed part of an array has more than one... <a href="00776.html" target="topic">more</a> </div></td></tr><tr>
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<a href="00777.html" target="topic">E.6.7 Canonical representation of packed arrays</a> </div></td><td class="Element206" valign="top" width="50%">
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The Direct Programming Interface defines the canonical representation of packed 2-state (type svBitVec32) and 4-state arrays (type svLogicVec32). This canonical representation is derived from on the Verilog legacy PLI’s avalue/bvalue representation of 4-state vectors. Library functions provide the translation between the representation used in a simulator and the canonical representation of packed arrays.<br><br>A packed array is represented as an array of one or more elements (of type svBitVec32 for 2-state values and svLogicVec32 for 4-state values), each element representing a group of 32 bits.The first element of an array contains the 32 least-significant bits, next element contains the 32... <a href="00777.html" target="topic">more</a> </div></td></tr></table></div></div>
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