svpwm_overmodulation_tb.vhd

来自「这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测」· VHDL 代码 · 共 111 行

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-- Company: 
-- Engineer:
--
-- Create Date:   19:58:04 02/03/2007
-- Design Name:   svpwm_overmodulation
-- Module Name:   E:/FPGA/ISEexample/svpwm_overmodulation/svpwm_overmodulation_tb.vhd
-- Project Name:  svpwm_overmodulation
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: svpwm_overmodulation
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY svpwm_overmodulation_tb_vhd IS
END svpwm_overmodulation_tb_vhd;

ARCHITECTURE behavior OF svpwm_overmodulation_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT svpwm_overmodulation
	PORT(
		clk : IN std_logic;
		reset : IN std_logic;
		en : IN std_logic;
		ta : IN std_logic_vector(17 downto 0);
		tb : IN std_logic_vector(17 downto 0);          
		n_ta : OUT std_logic_vector(17 downto 0);
		n_tb : OUT std_logic_vector(17 downto 0);
		n_t0 : OUT std_logic_vector(17 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';
	SIGNAL en :  std_logic := '1';
	SIGNAL ta :  std_logic_vector(17 downto 0) := (others=>'0');
	SIGNAL tbb :  std_logic_vector(17 downto 0) := (others=>'0');

	--Outputs
	SIGNAL n_ta :  std_logic_vector(17 downto 0);
	SIGNAL n_tb :  std_logic_vector(17 downto 0);
	SIGNAL n_t0 :  std_logic_vector(17 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: svpwm_overmodulation PORT MAP(
		clk => clk,
		reset => reset,
		en => en,
		ta => ta,
		tb => tbb,
		n_ta => n_ta,
		n_tb => n_tb,
		n_t0 => n_t0
	);

   reset	<= '1' after 40 ns;
	clk	<= not clk after 10 ns;
	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here
		ta <=  "000000000000000011";
		tbb <= "000000000111111111";
		wait for 40 ns;
		en <= '0';
		wait for 40 ns;
		en <= '1';
		--wait for 200 ns;
		--ta <= "00010100";
		--tbb <= "00001010";
		--wait for 40 ns;
		--en <= '0';
		--wait for 40 ns;
		--en <= '1';
		--wait for 200 ns;
		--ta <= "00011001";
		--tbb <= "00011001";
		--wait for 40 ns;
		--en <= '0';
		--wait for 40 ns;
		--en <= '1';		
		wait; -- will wait forever
	END PROCESS;

END;