svpwm_fsm_tb.vhd

这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   20:34:50 01/29/2007
-- Design Name:   svpwm_fsm
-- Module Name:   E:/FPGA/ISEexample/generate/tb.vhd
-- Project Name:  generate
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: svpwm_fsm
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_vhd IS
END tb_vhd;

ARCHITECTURE behavior OF tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT svpwm_fsm
	PORT(
		reset : IN std_logic;
		clk : IN std_logic;
		syncpulse : IN std_logic;
		asymstate : IN std_logic;
		Vx : IN std_logic_vector(2 downto 0);
		Vy : IN std_logic_vector(2 downto 0);
		t0_in : IN std_logic_vector(17 downto 0);
		ta_in : IN std_logic_vector(17 downto 0);
		tb_in : IN std_logic_vector(17 downto 0);          
		vec_out : OUT std_logic_vector(2 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL reset :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL syncpulse :  std_logic := '0';
	SIGNAL asymstate :  std_logic := '1';
	SIGNAL Vx :  std_logic_vector(2 downto 0) := "100";
	SIGNAL Vy :  std_logic_vector(2 downto 0) := "110";
	SIGNAL t0_in :  std_logic_vector(17 downto 0) := "000000000101100000";
	SIGNAL ta_in :  std_logic_vector(17 downto 0) := "000000000000100111";
	SIGNAL tb_in :  std_logic_vector(17 downto 0) := "000000000001101101";
												--	 123456789012345678			
	--Outputs
	SIGNAL vec_out :  std_logic_vector(2 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: svpwm_fsm PORT MAP(
		reset => reset,
		clk => clk,
		syncpulse => syncpulse,
		asymstate => asymstate,
		Vx => Vx,
		Vy => Vy,
		t0_in => t0_in,
		ta_in => ta_in,
		tb_in => tb_in,
		vec_out => vec_out
	);

	reset	<= '1' after 40 ns;
	clk	<= not clk after 10 ns;

	tb : PROCESS
	BEGIN
		-- Wait 100 ns for global reset to finish
			wait for 100 ns;
			wait for 40 ns;
			syncpulse <= '1';
			wait for  40 ns;
			syncpulse <= '0';
			--wait for 200 ns;
			--t0_in <= "00000100";
			--ta_in <= "00000010";
			--tb_in <= "00000001";
			--asymstate <= '0';			
			--wait for 400 ns; 
			--syncpulse <= '1'; 
            --wait for  40 ns; 
            --syncpulse <= '0';
		-- Place stimulus here
		wait; -- will wait forever
	END PROCESS;
END;