svpwm_top_tb1.vhd

这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY svpwm_top_tb IS
	Generic (
	 		alfa_beta_width : integer range 1 to 20 := 18
	 		
	 		);
END svpwm_top_tb;

ARCHITECTURE behavior OF svpwm_top_tb IS 

	COMPONENT svpwm_top
	PORT(
		--
		-- input port
		--
		clk    : in std_logic;
    	reset  : in std_logic;
    	alfa   : in std_logic_vector(alfa_beta_width-1 downto 0);
    	beta   : in std_logic_vector(alfa_beta_width-1 downto 0);
    	en	   : in std_logic;
    	asymstate : in std_logic;
		--		
		-- output port
		--
		vec_out : out std_logic_vector(2 downto 0);
		u_top   : out std_logic;
    	u_bot   : out std_logic;
    	v_top   : out std_logic;
    	v_bot   : out std_logic;
    	w_top   : out std_logic;
    	w_bot   : out std_logic	
		);
	END COMPONENT;
	--COMPONENT table
	--PORT(
	--	--
	--	-- input port
	--	--
	--	clk				: in std_logic;
	--	reset			: in std_logic;
	--	add				: in std_logic_vector( 5 downto 0);
	--	--		
	--	-- output port
	--	--
	--	data			: out std_logic_vector ( 17 downto 0)
	--	);
	--END COMPONENT;

		--
		-- input port signal
		--
		signal clk    : std_logic :='0';
    	signal reset  : std_logic :='0';
    	signal alfa   : std_logic_vector(alfa_beta_width-1 downto 0) := (others => '0');
    	signal beta   : std_logic_vector(alfa_beta_width-1 downto 0) := (others => '0');
    	signal en	  : std_logic :='0';
    	signal asymstate :  std_logic :='1';
    	--signal add  	: std_logic_vector( 5 downto 0) := "000000";
		--		
		-- output port signal
		--
		signal vec_out : std_logic_vector(2 downto 0);
		signal u_top   : std_logic;
    	signal u_bot   : std_logic;
    	signal v_top   : std_logic;
    	signal v_bot   : std_logic;
    	signal w_top   : std_logic;
    	signal w_bot   : std_logic;
    	--signal data 	:std_logic_vector ( 17 downto 0);
BEGIN

	uut: svpwm_top PORT MAP(
		--
		-- input port
		--
		clk    => clk,
		reset  => reset,
		alfa   => alfa,
		beta   => beta,
		en	   => en,
		asymstate => asymstate,
		--		
		-- output port
		--
		vec_out => vec_out,
		u_top => u_top,
		u_bot => u_bot,
		v_top => v_top,
		v_bot => v_bot,
		w_top => w_top,
		w_bot => w_bot
		
		);
	--rom: table PORT MAP(
	--	--
	--	-- input port
	--	--
	--	clk	  => clk  , 
	--	reset => reset,
	--	add	  => add  ,
	--	--		
	--	-- output port
	--	--
	--	data => data
	--);

	reset	<= '1' after 40 ns;
	clk	<= not clk after 10 ns;

	tb : PROCESS
	BEGIN
		-- Wait 100 ns for global reset to finish
			wait for 100 ns;
			en <= '1';
			alfa <= "000000000010011110";
			beta <= "000000000000010010";
			--add <= "000001";
			--alfa <= data(17) & "000000000" & data(16 downto 9);
			--beta <= data(8) & "000000000" & data (7 downto 0);
		-- wait for 80000 ns;             			                 
		-- alfa <= "100000000000101000";
		-- beta <= "100000000000001000";
		-- Place stimulus here
		wait; -- will wait forever
	END PROCESS;
END;