svpwm_fsm.vhd

这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序

----------------------------------------------------------------------------------
-- Company:				SYTU.CC
-- Engineer:  			Hejiong
-- 
-- Create Date:    	2007-02-04
-- Design Name: 	 	FSM
-- Module Name:    	FSM - Behavioral 
-- Project Name: 		SVPWM
-- Target Devices: 	Spartan3E
-- Tool versions: 	ISE 8.2i
--
-- Description: 
--   The FSM in svpwm generate the top signal of the UVW for the IGBTs in the converter. 
-- s0: 
--		last time : t0_in for symmetry  or 2*t0_in for asymmetry
-- 	output vector : V0 -- 000 --zero vector
-- s1:
--    last time : ta_in for symmetry  or 2*ta_in for asymmetry
--    output vector : Vx -- the front vector of the current sector
-- s2:
--    last time : tb_in for symmetry  or 2*tb_in for asymmetry
--    output vector : Vy -- the bect vector of the current sector
-- s3:
--    last time : 2*t0
--		output vector : V1 -- 111 --zero vector
-- port:
--		reset : the reset signal : '0':clear
--		clk : the clock signal
--		syncpulse : synchronization pulse : '0':enable
--		asymstate : symmetry state signal : '0':asymmetry ; '1':symmetry
--		Vx : the front vector of the current sector
--		Vy : the bect vector of the current sector
--		t0_in : the last time of state "s0" and "s3"
--		ta_in : the last time of state "s1"
--		tb_in : the last time of state "s2"
--		vec_out : the output of the vector
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.02
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity svpwm_fsm is
	 Generic (
			V0				: std_logic_vector (2 downto 0) := "000";
			V1				: std_logic_vector (2 downto 0) := "111";
			asym_state_6 	: integer :=6;
			asym_state_3 	: integer :=3;
			cnt_width 		: integer :=18
	 );
	 Port (
		 	--
		 	-- input port
		 	--
		 	reset		: in std_logic;
			clk			: in std_logic;
			syncpulse 	: in STD_LOGIC;
			asymstate   : in std_logic;
			Vx			: in std_logic_vector (2 downto 0) := "100";
			Vy 			: in std_logic_vector (2 downto 0) := "110";
			t0_in		: in std_logic_vector (cnt_width-1 downto 0);
			ta_in		: in std_logic_vector (cnt_width-1 downto 0);
			tb_in		: in std_logic_vector (cnt_width-1 downto 0);

			--
			-- output port
			--
			vec_out		: out std_logic_vector (2 downto 0)			
		);
end svpwm_fsm;

architecture Behavioral of svpwm_fsm is
type state is (
		s0,
		s1,
		s2,
		s3
	);

signal b_syncpulse 			: std_logic;
signal b_syncpulse_delay 	: std_logic;
signal en_signal 			: std_logic;
signal sp_state 			: std_logic := '0';
signal currentstate			: state := s0; 	
signal laststate			: state := s0;
signal asym					: std_logic;
signal vec_cnt				: std_logic_vector ( cnt_width-1 downto 0);
signal state_cnt			: std_logic_vector ( 3 downto 0);
signal Vx_s					: std_logic_vector (2 downto 0) := "100";
signal Vy_s					: std_logic_vector (2 downto 0) := "110";
signal t0	 				: std_logic_vector ( cnt_width-1 downto 0);
signal ta	 				: std_logic_vector ( cnt_width-1 downto 0);
signal tb	 				: std_logic_vector ( cnt_width-1 downto 0);

begin
	-- port buffer
	process (clk) begin
		if (rising_edge(clk)) then
			if (reset = '0') then
				b_syncpulse <= '0';
			else
				b_syncpulse <= syncpulse;
			end if;
		end if;
	end process;
	
	-- start the FSM
	process (clk) begin
		if (rising_edge(clk)) then
			if (reset ='0') then
				en_signal <= '0';                         
				b_syncpulse_delay <= '0';                 

			else
				b_syncpulse_delay <= b_syncpulse;
				if (b_syncpulse = '0' and b_syncpulse_delay = '1') then --falling_edge
				--if (b_syncpulse = '1' and b_syncpulse_delay = '0') then --rising_edge
					en_signal <= '1';
				end if;
			end if;
			if (en_signal = '1') then 

				en_signal <= '0';
			end if;
		end if;
	end process;
	
	-- the FSM
	process (clk) begin
		if (rising_edge(clk)) then
			if (reset = '0') then
				sp_state	 <= '0';
				currentstate <= s0; 	                           				
				laststate	 <= s0;                                 
				asym		 <= '0';
				vec_cnt		 <= (others => '0');
				state_cnt	 <= "0000";
				Vx_s		 <= "000";
				Vy_s		 <= "000";
				t0	 		 <= (others => '0');
				ta	 		 <= (others => '0');
				tb	 		 <= (others => '0');								
			else
				if (en_signal = '1') then
					sp_state <= '1';
					currentstate <= s0; 	                           				
					laststate	 <= s0;                                 
					asym		 <= asymstate;
					vec_cnt		 <= (others => '0');
					state_cnt	 <= "0000";
					Vx_s		 <= Vx;
					Vy_s		 <= Vy;
					t0	 		 <= ('0' & t0_in(cnt_width-1 downto 1)) + 1;
					ta	 		 <= ta_in + 1;
					tb	 		 <= tb_in + 1;
				elsif (sp_state = '1') then
					case currentstate is
						when s0 =>
							vec_cnt <= vec_cnt+1;							
							if (asym = '1') then
								if (conv_integer(state_cnt) = asym_state_6) then
									sp_state <= '0';
									state_cnt <=(others => '0');
								end if;
								if (vec_cnt = (('0' & t0)-1) ) then
									vec_cnt <= (others => '0');
									laststate <= s0;
									currentstate <= s1;
									state_cnt <= state_cnt+1;
								end if;
							else -- asym = '0'
								if (conv_integer(state_cnt) = asym_state_3 ) then
									sp_state <= '0';
									state_cnt <=(others => '0');
								end if;								
								if (laststate = s0) then
									vec_cnt <= (others => '0');
									laststate <= s0;
									currentstate <= s3;
									state_cnt <= state_cnt+1;
								end if;
							end if;

						when s1 =>
							vec_cnt <= vec_cnt+1;
							if (asym = '1') then
								if (vec_cnt = (('0' & ta)-1) and laststate = s0) then
									vec_cnt <= (others => '0');
									laststate <= s1;
									currentstate <= s2;
									state_cnt <= state_cnt+1;
								end if;							
								if (vec_cnt = (('0' & ta)-1) and laststate = s2) then
									vec_cnt <= (others => '0');
									laststate <= s1;
									currentstate <= s0;
									state_cnt <= state_cnt+1;
								end if;
							elsif (vec_cnt = ((ta & '0')-1) and laststate = s2) then
									vec_cnt <= (others => '0');
									laststate <= s1;
									currentstate <= s0;
									state_cnt <= state_cnt;
							end if;

						when s2 =>
							vec_cnt <= vec_cnt+1;							
							if (asym = '1') then
								if (vec_cnt = (('0' & tb)-1) and laststate = s1) then
									vec_cnt <= (others => '0');
									laststate <= s2;
									currentstate <= s3;
									state_cnt <= state_cnt+1;
								end if;
								if (vec_cnt = (('0' & tb)-1) and laststate = s3) then
									vec_cnt <= (others => '0');
									laststate <= s2;
									currentstate <= s1;
									state_cnt <= state_cnt+1;
								end if;
							elsif (vec_cnt = ((tb & '0')-1) and laststate = s3) then
									vec_cnt <= (others => '0');
									laststate <= s2;
									currentstate <= s1;
									state_cnt <= state_cnt+1;
							end if;
	
						when s3 =>
							vec_cnt <= vec_cnt+1;							
							if (asym = '1') then
								if (vec_cnt = ((t0 & '0')-1)) then
									vec_cnt <= (others => '0');
									laststate <= s3;
									currentstate <= s2;
									state_cnt <= state_cnt+1;
								end if;
							elsif (vec_cnt = ((t0 & '0')-1)) then
									vec_cnt <= (others => '0');
									laststate <= s3;
									currentstate <= s2;
									state_cnt <= state_cnt+1;
							end if;
	
						when others => 
									   laststate <= s0;
									   currentstate <= s0;
					end case;
				end if;
			end if;
		end if;
	end process;
	
	-- the output of the FSM
	process(clk) begin
		if (rising_edge(clk)) then
			if (reset = '0') then
				vec_out <= "000";
			else
				case currentstate is     
					when s0     =>       
						vec_out <= V0;   
					when s1     =>       
						vec_out <= Vx_s; 
					when s2     =>       
						vec_out <= Vy_s; 
					when s3     =>       
						vec_out <= V1;   
					when others =>       
						vec_out <= "000";
				end case;
			end if;
		end if;
	end process;

end Behavioral;