syncpulse_gen.vhd

这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity syncpulse_gen is

	Generic (
		C_COUNTER_WIDTH	: integer := 12;
		ts				: integer := 5 
	);	

    Port ( 
    	--
    	-- input signal
    	--
		clk		 : in std_logic;
		reset	 : in std_logic;
		ena 	 : in std_logic;
		--
		-- output signal
		--
		syncpulse : out std_logic
	);

end syncpulse_gen;

architecture Behavioral of syncpulse_gen is
	-- buffer of the input port
	signal b_ena		: std_logic;
	-- buffer of the output port
	signal b_syncpulse	: std_logic :='0';
	-- internal signals
	signal count		: std_logic_vector(C_COUNTER_WIDTH-1 downto 0 ) := (others => '0');
	signal down			: std_logic := '0';

begin
	-- initial
	process (clk) begin
		if (rising_edge(clk)) then
			if (reset = '0') then 
				b_ena <= '0';
			else
				b_ena <= ena;
			end if;
		end if;
	end process;
	-- syncpulse generate
	process (reset, clk) begin
		if (clk'event and clk = '1' ) then
			if ( reset = '0' ) then
				count <= (others => '0' );
				down <= '0';
			else
				if (b_ena = '1') then
					if (down = '0') then
						count <= count+1;
					else
						count <= count-1;
					end if;
					if (conv_integer(count) = ts) then
						down <= '1';
					end if;
					if (down = '1' and conv_integer(count) = 1) then
						down <= '0';
						b_syncpulse <= '1';
					end if;
					if (b_syncpulse = '1') then
						b_syncpulse <= '0';
					end if;
				end if;
			end if;
		end if;
	end process;
	syncpulse <= not b_syncpulse;	--'0':enable
	--syncpulse <= b_syncpulse;	--'1':enable
end Behavioral;