svpwm_top.vhd

这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity svpwm_top is
	 Generic (
	 		alfa_beta_width : integer range 1 to 20 := 18
	 		
	 		);

    Port (
    	--
    	-- input port
    	--
    	clk    : in std_logic;
    	reset  : in std_logic;
    	en	   : in std_logic;
    	asymstate : in std_logic;
    	--
    	-- output port
    	--
    	vec_out : out std_logic_vector(2 downto 0);
    	u_top   : out std_logic;
    	u_bot   : out std_logic;
    	v_top   : out std_logic;
    	v_bot   : out std_logic;
    	w_top   : out std_logic;
    	w_bot   : out std_logic    	
    	);
end svpwm_top;
        
architecture Behavioral of svpwm_top is
	--
	-- input port buffer
	--
		signal b_en     : std_logic;
		signal b_alfa   : std_logic_vector (alfa_beta_width-1 downto 0);
		signal b_beta	: std_logic_vector (alfa_beta_width-1 downto 0);
		signal alfa   : std_logic_vector (alfa_beta_width-1 downto 0);
		signal beta	: std_logic_vector (alfa_beta_width-1 downto 0);
		signal b_asymstate: std_logic;
	--
	-- output port buffer
	--
		signal b_vec_out : std_logic_vector (2 downto 0);
		signal b_u_top   : std_logic; 
		signal b_u_bot   : std_logic; 
		signal b_v_top   : std_logic; 
		signal b_v_bot   : std_logic; 
		signal b_w_top   : std_logic;
		signal b_w_bot   : std_logic;
	--
	-- internal signals
	--
		signal b_ta : std_logic_vector (alfa_beta_width-1 downto 0);
		signal b_tb : std_logic_vector (alfa_beta_width-1 downto 0);
		signal b_n_ta : std_logic_vector (alfa_beta_width-1 downto 0);
		signal b_n_tb : std_logic_vector (alfa_beta_width-1 downto 0);
		signal b_n_t0 : std_logic_vector (alfa_beta_width-1 downto 0);
		signal b_Vx : std_logic_vector (2 downto 0);
		signal b_Vy : std_logic_vector (2 downto 0);
		signal b_syncpulse : std_logic;
		signal b_syncpulse_d : std_logic;
		signal add : std_logic_vector (5 downto 0);
	--
	-- components
	--
	
	-- sector_scan 
	component sector_scan is
	  port(
	  		-- input port
	  		clk   		:   in std_logic;
	  		reset  	    :   in std_logic;
	        en    		:   in std_logic;
	        ma    		:   in std_logic_vector(alfa_beta_width-1 downto 0);
	        mb    		:   in std_logic_vector(alfa_beta_width-1 downto 0);
	        syn_pulse 	:   in std_logic;
	        -- output port
	        ta        	:   out std_logic_vector(alfa_beta_width-1 downto 0);
	        tb        	:   out std_logic_vector(alfa_beta_width-1 downto 0);
	        Vx			:   out std_logic_vector(2 downto 0);
	        Vy			:   out std_logic_vector(2 downto 0)
	        );
	end component;
	
	-- svpwm_overmodulation
	component svpwm_overmodulation is
		 generic (
					  last_time_width : integer range 1 to 64 := alfa_beta_width;
		 			  ts : std_logic_vector(alfa_beta_width-1 downto 0):= "000010011100010000"		--to be changed----10000		 			  													   
					 );
	    Port ( clk 		: in   STD_LOGIC;
	           reset 	: in   STD_LOGIC;
			   en 		: in   STD_LOGIC;
	           ta 		: in   STD_LOGIC_VECTOR (last_time_width-1 downto 0);
	           tb 		: in   STD_LOGIC_VECTOR (last_time_width-1 downto 0);
	           n_ta 	: out  STD_LOGIC_VECTOR (last_time_width-1 downto 0);
	           n_tb 	: out  STD_LOGIC_VECTOR (last_time_width-1 downto 0);
	           n_t0 	: out  STD_LOGIC_VECTOR (last_time_width-1 downto 0)
				  );
	end component;
	
	-- svpwm_fsm
	component svpwm_fsm is
		 Generic (
				V0				: std_logic_vector (2 downto 0) := "000";
				V1				: std_logic_vector (2 downto 0) := "111";
				asym_state_6 	: integer :=6;
				asym_state_3 	: integer :=3;
				cnt_width 		: integer :=alfa_beta_width
		 );
		 Port ( 		
			 	--
			 	-- input port
			 	--
			 	reset		: in std_logic;
				clk			: in std_logic;
				syncpulse 	: in STD_LOGIC;
				asymstate   : in std_logic;
				Vx			: in std_logic_vector (2 downto 0) := "100";
				Vy 			: in std_logic_vector (2 downto 0) := "110";
				t0_in		: in std_logic_vector (cnt_width-1 downto 0);
				ta_in		: in std_logic_vector (cnt_width-1 downto 0);
				tb_in		: in std_logic_vector (cnt_width-1 downto 0);	
				--
				-- output port
				--
				vec_out		: out std_logic_vector (2 downto 0)			
			);
	end component;
	
	-- table
	component table is
		Port(
		--
		-- input port
		--
		clk				: in std_logic;
		reset			: in std_logic;
		add				: in std_logic_vector( 5 downto 0);
		--
		-- output port
		--		
		datax			: out std_logic_vector ( 17 downto 0);
		datay			: out std_logic_vector ( 17 downto 0)
	);
	end component;
		
	-- syncpulse_gen
	component syncpulse_gen is

	Generic (
		C_COUNTER_WIDTH	: integer := alfa_beta_width;
		ts				: integer := 5000                 ----to be changed---------------
	);

    Port ( 
    	--
    	-- input signal
    	--
		clk		 : in std_logic;
		reset	 : in std_logic;
		ena 	 : in std_logic;
		--
		-- output signal
		--
		syncpulse : out std_logic
	);

	end component;
	
--	 deadzone
	component deadzone is
		 Generic (
		 		count_width : integer range 1 to 8 :=4; 
		 		deadtime    : integer range 1 to 128 := 10
		 		);
	
	    Port (
	    	--
	    	-- input port
	    	--
	    	clk		: in std_logic;
	    	reset   : in std_logic;    	
	    	pwm_in  : in std_logic;
	    	
	    	--
	    	-- output port
	    	--
	    	pwm_top  : out std_logic;
	    	pwm_bot  : out std_logic
	    	
	    	);
	end component;

begin
	process(clk) begin
		if (rising_edge(clk)) then
			if (reset = '0') then
				b_en <= '0';
				b_alfa <= (others =>'0');
				b_beta <= (others =>'0');                   
				b_asymstate <= '0';				
			else
				if (en = '1') then
					b_en <= en;
					b_asymstate <= asymstate;
					b_alfa <= alfa;
					b_beta <= beta;
				end if;
			end if;
		end if;
	end process;
	
	process (clk) begin
		if (rising_edge(clk)) then 
			b_syncpulse_d <= b_syncpulse;
		end if;
	end process;
	
	process (clk) begin
		if (rising_edge(clk)) then
			if (reset = '0') then
				add <= "000000";
			else
				if (b_syncpulse = '0' and b_syncpulse_d = '1') then
					add <= add + 1;
				end if;
			end if;
		end if;
	end process;
	
	
	
	vec_out <= b_vec_out;
	u_top  <= b_vec_out(2);
	u_bot  <= not b_vec_out(2);
	v_top  <= b_vec_out(1);
	v_bot  <= not b_vec_out(1);
	w_top  <= b_vec_out(0);
	w_bot  <= not b_vec_out(0);	
	sector: sector_scan PORT MAP(
			-- input port 
	  		clk  		=> clk,
	  		reset       => reset,
	        en    		=> b_en,
	        ma    		=> b_alfa,
	        mb    		=> b_beta,
	        syn_pulse 	=> b_syncpulse,
	        -- output port
	        ta  	=>b_ta,      	
	        tb  	=>b_tb, 	
	        Vx		=>b_Vx,		
	        Vy		=>b_Vy		
	        );
	fsm: svpwm_fsm port map(
			--
			-- input port
			--
			reset		=> reset,
			clk			=> clk,
			syncpulse 	=> b_syncpulse,
			asymstate   => b_asymstate,
			Vx			=> b_Vx,
			Vy 			=> b_Vy,
			t0_in		=> b_n_t0,
			ta_in		=> b_n_ta,
			tb_in		=> b_n_tb,
			--
			-- output port
			--
			vec_out		=> b_vec_out
			);
	syncpulse : syncpulse_gen port map(
			--                       
			-- input signal          
			--                       
			clk		 => clk,
			reset	 => reset,
			ena 	 => b_en,
			--                       
			-- output signal         
			--                       
			syncpulse => b_syncpulse			
			);
	overmodule : svpwm_overmodulation port map(
			clk 	=> clk,
			reset 	=> reset,
			en 		=> b_en,
			ta 		=> b_ta,
			tb 		=> b_tb,
			n_ta 	=> b_n_ta,
			n_tb 	=> b_n_tb,
			n_t0 	=> b_n_t0
			);
	u_deadzone : deadzone port map(
			--                       
			-- input port            
			--                       
			clk		=> clk,
			reset   => reset,
			pwm_in  => b_vec_out(2),
			--                       
			-- output port           
			--                       
			pwm_top  => b_u_top,
			pwm_bot  => b_u_bot
			);
	v_deadzone : deadzone port map(
			--                       
			-- input port            
			--                       
			clk		=> clk,
			reset   => reset,
			pwm_in  => b_vec_out(1),
			--                       
			-- output port           
			--                       
			pwm_top =>  b_v_top,
			pwm_bot =>  b_v_bot
			);
	w_deadzone : deadzone port map(
			--                       
			-- input port            
			--                       
			clk		=> clk,
			reset   => reset,
			pwm_in  => b_vec_out(0),
			--                       
			-- output port           
			--                       
			pwm_top  => b_w_top,
			pwm_bot  => b_w_bot
			);
	rom: table PORT MAP(
		--
		-- input port
		--
		clk	  => clk  , 
		reset => reset,
		add	  => add  ,
		--		
		-- output port
		--
		datax => alfa,
		datay => beta		
	);
	
end Behavioral;