table.vhd

这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity table is
	Port(
		--
		-- input port
		--
		clk				: in std_logic;
		reset			: in std_logic;
		add				: in std_logic_vector( 5 downto 0);
		--
		-- output port
		--
		datax			: out std_logic_vector ( 17 downto 0);
		datay			: out std_logic_vector ( 17 downto 0)
	);
end table;

architecture Behavioral of table is

		type memory is array (0 to 63) of std_logic_vector(17 downto 0);
		constant table : memory := (
		--  "+00000000+00000000","+00000000+00000000","+00000000+00000000","+00000000+00000000",
			"010011111000000010","010011110000010010","010011100000100001","010011000000110001",
			"010010010000111111","010001011001001101","010000011001011011","001111001001100111",			
			"001101111001110011","001100011001111101","001010110010000110","001001000010001110",
			"000111010010010100","000101011010011001","000011100010011101","000001100010011111",
			"100000010010011111","100010010010011110","100100001010011100","100110001010011000",
			"100111111010010010","101001101010001011","101011011010000011","101100111001111001",
			"101110011001101111","101111101001100011","110000110001010110","110001110001001000",
			"110010100000111010","110011001000101011","110011101000011100","110011111000001100",
			"110011111100000010","110011110100010010","110011100100100001","110011000100110001",
			"110010010100111111","110001011101001101","110000011101011011","101111001101100111",
			"101101111101110011","101100011101111101","101010110110000110","101001000110001110",
			"100111010110010100","100101011110011001","100011100110011101","100001100110011111",
			"000000010110011111","000010010110011110","000100001110011100","000110001110011000",
			"000111111110010010","001001101110001011","001011011110000011","001100111101111001",
			"001110011101101111","001111101101100011","010000110101010110","010001110101001000",
			"010010100100111010","010011001100101011","010011101100011100","010011111100001100"			
		);
		constant table1 : memory := (
		--  "+00000000+00000000","+00000000+00000000","+00000000+00000000","+00000000+00000000",
"001111111000000010","001111111000001110","001111101000011011","001111001000100111",
"001110101000110011","001101111000111110","001101001001001000","001100001001010010",
"001011000001011100","001001111001100100","001000101001101011","000111010001110001",
"000101110001110111","000100011001111011","000010110001111101","000001010001111111",
"100000010001111111","100001110001111111","100011011001111101","100100111001111001",
"100110011001110101","100111110001101111","101001000001101001","101010010001100001",
"101011100001011000","101100100001001111","101101011001000101","101110001000111010",
"101110111000101110","101111011000100011","101111101000010110","101111111000001010",
"101111111100000010","101111111100001110","101111101100011011","101111001100100111",
"101110101100110011","101101111100111110","101101001101001000","101100001101010010",
"101011000101011100","101001111101100100","101000101101101011","100111010101110001",
"100101110101110111","100100011101111011","100010110101111101","100001010101111111",
"000000010101111111","000001110101111111","000011011101111101","000100111101111001",
"000110011101110101","000111110101101111","001001000101101001","001010010101100001",
"001011100101011000","001100100101001111","001101011101000101","001110001100111010",
"001110111100101110","001111011100100011","001111101100010110","001111111100001010"
		);

		
begin
	process(clk) begin
		if (rising_edge(clk)) then
			if (reset = '0') then
				datax <= (others => '0');
				datay <= (others => '0');
			else
				datax <= table1(conv_integer (add))(17) & "000000000" & table1(conv_integer (add))(16 downto 9);
				datay <= table1(conv_integer (add))(8) & "000000000" & table1(conv_integer (add)) (7 downto 0);				
			end if;
		end if;
	end process;
end Behavioral;