svpwm_overmodulation.vhd

这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序

----------------------------------------------------------------------------------
-- Company: 		 SYTU
-- Engineer: 		 Hejiong
-- 
-- Create Date:    13:55:48 01/31/2007 
-- Design Name:    overmodulation
-- Module Name:    svpwm_overmodulation - Behavioral 
-- Project Name:   SVPWM
-- Target Devices: 
-- Tool versions: 
--
-- Description: 
--   The overmodulation module get the duration, which has been calculated by previous modules, 
-- to deal with the overmodulation situation, and then give the processed duration, with which
-- to control the converter.
-- port:
--		reset : the reset signal : '0':clear
--		clk : the clock signal
--		en : the enable signal : '0':enable
--		ta : the duration calculated previous for the front vector of the current sector
--		tb : the duration calculated previous for the back vector of the current sector
--		n_ta : the duration processed for the front vector of the current sector
--		n_tb : the duration processed for the back vector of the current sector
--		n_t0 : the duration processed for the zero vector 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity svpwm_overmodulation is
	 generic ( 
				  last_time_width : integer range 1 to 64 := 18;
	 			  ts : std_logic_vector(17 downto 0):= "000000001111101000"
				 );
    Port ( clk 		: in   STD_LOGIC;
           reset 	: in   STD_LOGIC;
		   en 		: in   STD_LOGIC;
           ta 		: in   STD_LOGIC_VECTOR (last_time_width-1 downto 0);
           tb 		: in   STD_LOGIC_VECTOR (last_time_width-1 downto 0);
           n_ta 	: out  STD_LOGIC_VECTOR (last_time_width-1 downto 0);
           n_tb 	: out  STD_LOGIC_VECTOR (last_time_width-1 downto 0);
           n_t0 	: out  STD_LOGIC_VECTOR (last_time_width-1 downto 0)
			  );
end svpwm_overmodulation;

architecture Behavioral of svpwm_overmodulation is

signal ta_s 	  : std_logic_vector (last_time_width-1 downto 0) :=(others => '0');
signal tb_s 	  : std_logic_vector (last_time_width-1 downto 0) :=(others => '0');
signal n_ta_s 	  : std_logic_vector (last_time_width-1 downto 0) :=(others => '0');
signal n_tb_s 	  : std_logic_vector (last_time_width-1 downto 0) :=(others => '0');
signal n_t0_s 	  : std_logic_vector (last_time_width-1 downto 0) :=(others => '0');
signal t_over 	  : std_logic_vector (last_time_width-1 downto 0) :=(others => '0');
signal en_state   : std_logic := '0';
signal ta_and_tb  : std_logic_vector (last_time_width-1 downto 0 );

begin
process(clk, reset)
	begin
		if (reset = '0') then
			n_ta_s <= (others => '0');
			n_tb_s <= (others => '0');
			n_t0_s <= (others => '0');
			t_over <= (others => '0');
		elsif rising_edge(clk) then
			ta_s <= ta;
			tb_s <= tb;
			if (en = '1') then
				ta_and_tb <= ta_s + tb_s;
				if (ta_and_tb < '0' & ts(last_time_width-1 downto 1)) then
					n_ta_s <= ta_s;
					n_tb_s <= tb_s;
					n_t0_s <= '0' & ts(last_time_width-1 downto 1) - ta_and_tb;
				else
					if (ta_and_tb = '0' & ts(last_time_width-1 downto 1)) then
						n_ta_s <= ta_s;
						n_tb_s <= tb_s;
						n_t0_s <= (others => '0');
					else
						t_over <= ('0' & ta_and_tb(last_time_width-1 downto 1)) - ("00" & ts(last_time_width-1 downto 2));
						if (ta_s < t_over) then 
							n_ta_s <= (others => '0');
							n_tb_s <= '0' & ts(last_time_width-1 downto 1);
							n_t0_s <= (others => '0');
						elsif (tb_s < t_over) then
							n_tb_s <= (others => '0');
							n_ta_s <= '0' & ts(last_time_width-1 downto 1);             
							n_t0_s <= (others => '0');
						else
							n_ta_s <= ta_s - t_over;
							n_tb_s <= tb_s - t_over;
							n_t0_s <= (others => '0');
						end if;
					end if;
				end if;
			end if;
		end if;
		n_ta <= n_ta_s;
        n_tb <= n_tb_s;
        n_t0 <= n_t0_s;
	end process;
end Behavioral;