📄 sec_find_comp.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity sector_scan is
port( clk : in std_logic;
reset : in std_logic;
en : in std_logic;
ma : in std_logic_vector(17 downto 0);
mb : in std_logic_vector(17 downto 0);
syn_pulse : in std_logic;
ta : out std_logic_vector(17 downto 0);
tb : out std_logic_vector(17 downto 0);
Vx : out std_logic_vector(2 downto 0);
Vy : out std_logic_vector(2 downto 0)
);
end sector_scan;
architecture Behavioral of sector_scan is
signal data_a_in,data_b_in,data_a_3,data1,data2,data3,data4,data5:std_logic_vector(17 downto 0);
signal data_shift_a1,data_shift_a2 :std_logic_vector(17 downto 0);
signal ta_freq,tb_freq:std_logic_vector(35 downto 0);
signal sure :std_logic;
signal index_ab:std_logic_vector(1 downto 0):="00";
signal sector_pos:std_logic_vector(2 downto 0);
signal syn_pulse_delay : std_logic;
signal d,e,ta_s,tb_s: std_logic_vector(17 downto 0);
signal ts: std_logic_vector(17 downto 0) :="000000001111101000";
signal data_shift_b1,data_shift_b4,data_shift_b11,data_shift_b8:std_logic_vector(17 downto 0);
signal data_b_0433,data_b_0866,data_a_075:std_logic_vector(17 downto 0);
signal data_ma,data_mb:std_logic_vector(17 downto 0);
signal Vx_out :std_logic_vector(2 downto 0);
signal Vy_out :std_logic_vector(2 downto 0);
begin
-------input ma,mb-------- initial
--process(clk,ma,mb,en,reset)
-- begin
-- if (clk'event and clk='1') then
-- data_ma<=ma;
-- data_mb<=mb;
-- syn_pulse_delay<=syn_pulse;
-- if (reset='0') then
-- ta_s<=(others => '0');
-- tb_s<=(others => '0');
-- --Vx_out<="000";
-- Vy_out<="000";
-- else
-- if (en='1') then
-- if (syn_pulse='1' and syn_pulse_delay<='0') then
--
-- data_a_in <= '0' & data_ma(16 downto 0);
-- data_b_in <= '0' & data_mb(16 downto 0);
-- index_ab <= data_ma(17) & data_mb(17);
--
-- end if;
-- end if;
-- end if;
-- end if;
process(clk,ma,mb,en,reset) begin
-- if (reset='0') then
-- data_ma<=(others => '0');
-- data_mb<=(others => '0');
--ta_s<=(others => '0');
--tb<="00000000000000000";
--Vx_out<="000";
--Vy_out<="000";
--elsif (reset='1') then
if (clk'event and clk='1') then
if (reset = '0') then
data_ma <= ( others => '0');
data_mb <= ( others => '0');
data_a_in <= ( others => '0');
data_b_in <= ( others => '0');
index_ab <= ( others => '0');
syn_pulse_delay <= syn_pulse;
else
data_ma<=ma;
data_mb<=mb;
syn_pulse_delay<=syn_pulse;
if (en='1' and syn_pulse = '1' and syn_pulse_delay = '0') then
data_a_in <= '0' & data_ma(16 downto 0);
data_b_in <= '0' & data_mb(16 downto 0);
index_ab <= data_ma(17) & data_mb(17);
end if;
end if;
end if;
-- end if;
end process;
----------------------------------------------------------------------
process(data_a_in,clk) begin
if (clk'event and clk='1') then
--data1<= '0' & data_a_in(17 downto 1);
--data2<= "0000" & data_a_in(17 downto 4);
--data3<= "000000" & data_a_in(17 downto 6);
--data4<= "0000000000" & data_a_in(17 downto 10);
--data_a_3<=data1+data2+data3-data4;
data1 <= data_a_in(16 downto 0) & '0';
data2<= "00" & data_a_in(17 downto 2);
data3<= "000000" & data_a_in(17 downto 6);
data4<= "000000000" & data_a_in(17 downto 9);
data_a_3<=data1-data2-data3-data4;
end if;
end process;
process(data_a_3,clk) begin
if (data_a_3>=data_b_in) then
sure<='1';
else
sure<='0';
end if;
end process;
process(sure,index_ab) begin
case index_ab is
when "00" =>
if (sure='1') then
sector_pos<="000";
else
sector_pos<="001";
end if;
when "10" =>
if (sure='1') then
sector_pos<="011";
else
sector_pos<="010";
end if;
when "11" =>
if (sure='1') then
sector_pos<="100";
else
sector_pos<="101";
end if;
when others =>
if (sure='1') then
sector_pos<="111";
else
sector_pos<="110";
end if;
end case;
end process;
process(data_a_in,clk) begin
if (clk'event and clk='1') then
if (reset = '0') then
data_shift_a1 <= (others => '0');
data_shift_a2 <= (others => '0');
data_a_075 <= (others => '0');
else
data_shift_a1<='0' & data_a_in(17 downto 1);
data_shift_a2<="00" & data_a_in(17 downto 2);
data_a_075 <= data_shift_a1 + data_shift_a2;
end if;
end if;
end process;
process(data_b_in,clk) begin
if (clk'event and clk='1') then
if (reset = '0') then
data_shift_b1 <= (others => '0');
data_shift_b4 <= (others => '0');
data_shift_b8 <= (others => '0');
data_shift_b11 <= (others => '0');
data_b_0433 <= (others => '0');
else
data_shift_b1 <='0' & data_b_in(17 downto 1);
data_shift_b4 <="0000" & data_b_in(17 downto 4);
data_shift_b8 <="00000000" & data_b_in(17 downto 8);
data_shift_b11<="00000000000" & data_b_in(17 downto 11);
data_b_0433<=data_shift_b1-data_shift_b4-data_shift_b8-data_shift_b11;
end if;
end if;
end process;
process(data_b_0433,clk) begin
if (clk'event and clk='1') then
if (reset = '0') then
data_b_0866 <= (others => '0');
else
data_b_0866<=data_b_0433(16 downto 0) & '0';
end if;
end if;
end process;
process(sector_pos,clk) begin
if(rising_edge (clk)) then
if(reset = '0') then
ta_s <= (others => '0');
tb_s <= (others => '0');
Vx_out <= "000";
Vy_out <= "000";
else
case sector_pos is
when "000" =>
ta_s<=data_a_075-data_b_0433;
tb_s<=data_b_0866;
Vx_out<="100";
Vy_out<="110";
when "001" =>
tb_s<=data_b_0433-data_a_075;
ta_s<=data_b_0433+data_a_075;
Vy_out<="110";
Vx_out<="010";
when "010" =>
tb_s<=data_b_0433+data_a_075;
ta_s<=data_b_0433-data_a_075;
Vy_out<="110";
Vx_out<="010";
when "011" =>
ta_s<=data_b_0866;
--ta_s<=(others=>'0');
tb_s<=data_a_075-data_b_0433;
Vx_out<="010";
Vy_out<="011";
---data_b_0433
when "100" =>
tb_s<=data_b_0866;
ta_s<=data_a_075-data_b_0433;
Vy_out<="011";
Vx_out<="001";
when "111" =>
tb_s<=data_a_075-data_b_0433;
ta_s<=data_b_0866;
Vy_out<="101";
Vx_out<="100";
when "110" =>
ta_s<=data_b_0433-data_a_075;
tb_s<=data_b_0433+data_a_075;
Vx_out<="001";
Vy_out<="101";
when others =>
ta_s<=data_b_0433+data_a_075;
tb_s<=data_b_0433-data_a_075;
Vx_out<="001";
Vy_out<="101";
end case;
end if;
end if;
Vx<=Vx_out;
Vy<=Vy_out;
--ta<=ta_s;
--tb<=tb_s;
end process;
process(clk,ta_s) begin
if (clk'event and clk='1') then
tb<=tb_freq(25 downto 8);
ta<=ta_freq(25 downto 8);
end if;
-- if (reset = '0') then
-- ta_freq <= (others => '0');
-- tb_freq <= (others => '0');
-- else
-- ta_freq<=ta_s*ts;
-- tb_freq<=tb_s*ts;
-- end if;
end process;
MULT18X18_inst1 : MULT18X18SIO
generic map(
AREG => 1, -- Enable the input registers on the A port (1=on, 0=off)
BREG => 1, -- Enable the input registers on the B port (1=on, 0=off)
B_INPUT => "DIRECT", -- B cascade input "DIRECT" or "CASCADE"
PREG => 1
) -- Enable the input registers on the P port (1=on, 0=off)
port map(
BCOUT =>d , -- 18-bit cascade output
P => ta_freq, -- 36-bit multiplier output
A =>ta_s, -- 18-bit multiplier input
B => ts, -- 18-bit multiplier input
BCIN =>"000000000000000000", -- 18-bit cascade input
CEA => '1', -- Clock enable input for the A port
CEB => '1', -- Clock enable input for the B port
CEP => '1', -- Clock enable input for the P port
CLK => CLK, -- Clock input
RSTA => '0', -- Synchronous reset input for the A port
RSTB => '0', -- Synchronous reset input for the B port
RSTP => '0' -- Synchronous reset input for the P port
);
MULT18X18_inst2 : MULT18X18SIO
port map(
BCOUT =>e , -- 18-bit cascade output
P => tb_freq, -- 36-bit multiplier output
A =>tb_s, -- 18-bit multiplier input
B => ts, -- 18-bit multiplier input
BCIN =>"000000000000000000", -- 18-bit cascade input
CEA => '1', -- Clock enable input for the A port
CEB => '1', -- Clock enable input for the B port
CEP => '1', -- Clock enable input for the P port
CLK => CLK, -- Clock input
RSTA => '0', -- Synchronous reset input for the A port
RSTB => '0', -- Synchronous reset input for the B port
RSTP => '0' -- Synchronous reset input for the P port
);
end Behavioral;
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