watch.sim.rpt

一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S

+--------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                     ;
+---------------------------------------------+---------------------------------------------+------------------+
; Node Name                                   ; Output Port Name                            ; Output Port Type ;
+---------------------------------------------+---------------------------------------------+------------------+
; |watch|time:inst|\divclk:cnt[5]             ; |watch|time:inst|\divclk:cnt[5]             ; dataout          ;
; |watch|time:inst|clk1                       ; |watch|time:inst|clk1                       ; dataout          ;
; |watch|countdown:inst5|\pro1:sel_reg[0]     ; |watch|countdown:inst5|\pro1:sel_reg[0]     ; dataout          ;
; |watch|countdown:inst5|\pro1:sel_reg[1]     ; |watch|countdown:inst5|\pro1:sel_reg[1]     ; dataout          ;
; |watch|time:inst|\timecount:time_reg[0]     ; |watch|time:inst|\timecount:time_reg[0]     ; dataout          ;
; |watch|keyscan:inst8|treg2[0]               ; |watch|keyscan:inst8|treg2[0]               ; dataout          ;
; |watch|keyscan:inst8|treg1[0]               ; |watch|keyscan:inst8|treg1[0]               ; dataout          ;
; |watch|keyscan:inst8|treg2[1]               ; |watch|keyscan:inst8|treg2[1]               ; dataout          ;
; |watch|keyscan:inst8|treg1[1]               ; |watch|keyscan:inst8|treg1[1]               ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt1[0]        ; |watch|countdown:inst5|\pro1:cnt1[0]        ; dataout          ;
; |watch|time:inst|\timecount:time_reg[2]     ; |watch|time:inst|\timecount:time_reg[2]     ; dataout          ;
; |watch|keyscan:inst8|treg2[2]               ; |watch|keyscan:inst8|treg2[2]               ; dataout          ;
; |watch|keyscan:inst8|treg1[2]               ; |watch|keyscan:inst8|treg1[2]               ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt1[1]        ; |watch|countdown:inst5|\pro1:cnt1[1]        ; dataout          ;
; |watch|time:inst|\timecount:time_reg[3]     ; |watch|time:inst|\timecount:time_reg[3]     ; dataout          ;
; |watch|keyscan:inst8|treg2[3]               ; |watch|keyscan:inst8|treg2[3]               ; dataout          ;
; |watch|keyscan:inst8|treg1[3]               ; |watch|keyscan:inst8|treg1[3]               ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt1[2]        ; |watch|countdown:inst5|\pro1:cnt1[2]        ; dataout          ;
; |watch|time:inst|\timecount:time_reg[4]     ; |watch|time:inst|\timecount:time_reg[4]     ; dataout          ;
; |watch|keyscan:inst8|treg2[4]               ; |watch|keyscan:inst8|treg2[4]               ; dataout          ;
; |watch|keyscan:inst8|treg1[4]               ; |watch|keyscan:inst8|treg1[4]               ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt1[3]        ; |watch|countdown:inst5|\pro1:cnt1[3]        ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt2[0]        ; |watch|countdown:inst5|\pro1:cnt2[0]        ; dataout          ;
; |watch|keyscan:inst8|treg2[5]               ; |watch|keyscan:inst8|treg2[5]               ; dataout          ;
; |watch|keyscan:inst8|treg1[5]               ; |watch|keyscan:inst8|treg1[5]               ; dataout          ;
; |watch|time:inst|\timecount:time_reg[6]     ; |watch|time:inst|\timecount:time_reg[6]     ; dataout          ;
; |watch|keyscan:inst8|treg2[6]               ; |watch|keyscan:inst8|treg2[6]               ; dataout          ;
; |watch|keyscan:inst8|treg1[6]               ; |watch|keyscan:inst8|treg1[6]               ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt2[1]        ; |watch|countdown:inst5|\pro1:cnt2[1]        ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt2[2]        ; |watch|countdown:inst5|\pro1:cnt2[2]        ; dataout          ;
; |watch|time:inst|\timecount:time_reg[7]     ; |watch|time:inst|\timecount:time_reg[7]     ; dataout          ;
; |watch|keyscan:inst8|treg2[7]               ; |watch|keyscan:inst8|treg2[7]               ; dataout          ;
; |watch|keyscan:inst8|treg1[7]               ; |watch|keyscan:inst8|treg1[7]               ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt2[3]        ; |watch|countdown:inst5|\pro1:cnt2[3]        ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt3[0]        ; |watch|countdown:inst5|\pro1:cnt3[0]        ; dataout          ;
; |watch|time:inst|\timecount:time_reg[8]     ; |watch|time:inst|\timecount:time_reg[8]     ; dataout          ;
; |watch|keyscan:inst8|treg2[8]               ; |watch|keyscan:inst8|treg2[8]               ; dataout          ;
; |watch|keyscan:inst8|treg1[8]               ; |watch|keyscan:inst8|treg1[8]               ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt3[1]        ; |watch|countdown:inst5|\pro1:cnt3[1]        ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt3[2]        ; |watch|countdown:inst5|\pro1:cnt3[2]        ; dataout          ;
; |watch|time:inst|\timecount:time_reg[9]     ; |watch|time:inst|\timecount:time_reg[9]     ; dataout          ;
; |watch|keyscan:inst8|treg2[9]               ; |watch|keyscan:inst8|treg2[9]               ; dataout          ;
; |watch|keyscan:inst8|treg1[9]               ; |watch|keyscan:inst8|treg1[9]               ; dataout          ;
; |watch|countdown:inst5|\pro1:cnt3[3]        ; |watch|countdown:inst5|\pro1:cnt3[3]        ; dataout          ;
; |watch|display:inst6|bcd~5288               ; |watch|display:inst6|bcd~5288               ; dataout          ;
; |watch|time:inst|\timecount:time_reg[10]    ; |watch|time:inst|\timecount:time_reg[10]    ; dataout          ;
; |watch|keyscan:inst8|treg2[10]              ; |watch|keyscan:inst8|treg2[10]              ; dataout          ;
; |watch|keyscan:inst8|treg1[10]              ; |watch|keyscan:inst8|treg1[10]              ; dataout          ;
; |watch|display:inst6|bcd~5300               ; |watch|display:inst6|bcd~5300               ; dataout          ;
; |watch|time:inst|\timecount:time_reg[11]    ; |watch|time:inst|\timecount:time_reg[11]    ; dataout          ;
; |watch|keyscan:inst8|treg2[11]              ; |watch|keyscan:inst8|treg2[11]              ; dataout          ;
; |watch|keyscan:inst8|treg1[11]              ; |watch|keyscan:inst8|treg1[11]              ; dataout          ;
; |watch|display:inst6|bcd[3]                 ; |watch|display:inst6|bcd[3]                 ; dataout          ;
; |watch|keyscan:inst8|Mux31~347              ; |watch|keyscan:inst8|Mux31~347              ; pexpout          ;
; |watch|keyscan:inst8|Mux30~288              ; |watch|keyscan:inst8|Mux30~288              ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt1[1]~20     ; |watch|countdown:inst5|\pro1:cnt1[1]~20     ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt1[1]~22     ; |watch|countdown:inst5|\pro1:cnt1[1]~22     ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt1[2]~20     ; |watch|countdown:inst5|\pro1:cnt1[2]~20     ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt1[3]~13     ; |watch|countdown:inst5|\pro1:cnt1[3]~13     ; pexpout          ;
; |watch|time:inst|\timecount:time_reg[5]~26  ; |watch|time:inst|\timecount:time_reg[5]~26  ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt2[1]~20     ; |watch|countdown:inst5|\pro1:cnt2[1]~20     ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt2[1]~22     ; |watch|countdown:inst5|\pro1:cnt2[1]~22     ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt2[2]~20     ; |watch|countdown:inst5|\pro1:cnt2[2]~20     ; pexpout          ;
; |watch|time:inst|\timecount:time_reg[7]~26  ; |watch|time:inst|\timecount:time_reg[7]~26  ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt2[3]~13     ; |watch|countdown:inst5|\pro1:cnt2[3]~13     ; pexpout          ;
; |watch|time:inst|\timecount:time_reg[8]~25  ; |watch|time:inst|\timecount:time_reg[8]~25  ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt3[1]~416    ; |watch|countdown:inst5|\pro1:cnt3[1]~416    ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt3[1]~418    ; |watch|countdown:inst5|\pro1:cnt3[1]~418    ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt3[2]~21     ; |watch|countdown:inst5|\pro1:cnt3[2]~21     ; pexpout          ;
; |watch|time:inst|\timecount:time_reg[9]~25  ; |watch|time:inst|\timecount:time_reg[9]~25  ; pexpout          ;
; |watch|countdown:inst5|\pro1:cnt3[3]~608    ; |watch|countdown:inst5|\pro1:cnt3[3]~608    ; pexpout          ;
; |watch|display:inst6|bcd~5313               ; |watch|display:inst6|bcd~5313               ; pexpout          ;
; |watch|time:inst|\timecount:time_reg[10]~25 ; |watch|time:inst|\timecount:time_reg[10]~25 ; pexpout          ;
; |watch|display:inst6|bcd~5319               ; |watch|display:inst6|bcd~5319               ; pexpout          ;
; |watch|time:inst|\timecount:time_reg[11]~25 ; |watch|time:inst|\timecount:time_reg[11]~25 ; pexpout          ;
; |watch|display:inst6|bcd~5325               ; |watch|display:inst6|bcd~5325               ; pexpout          ;
; |watch|display:inst6|bcd~5330               ; |watch|display:inst6|bcd~5330               ; pexpout          ;
; |watch|~VCC~0                               ; |watch|~VCC~0                               ; dataout          ;
; |watch|display:inst6|bcd~5269sexp2bal       ; |watch|display:inst6|bcd~5269sexp2bal       ; dataout          ;
; |watch|display:inst6|bcd~5275sexp2bal       ; |watch|display:inst6|bcd~5275sexp2bal       ; dataout          ;
; |watch|KEYOUT[0]                            ; |watch|KEYOUT[0]                            ; padio            ;
; |watch|LED2                                 ; |watch|LED2                                 ; padio            ;
; |watch|BCD[2]                               ; |watch|BCD[2]                               ; padio            ;
; |watch|BCD[3]                               ; |watch|BCD[3]                               ; padio            ;
+---------------------------------------------+---------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Mar 12 09:47:45 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off watch -c watch
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      27.35 %
Info: Number of transitions in simulation is 774
Info: Vector file watch.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Processing ended: Wed Mar 12 09:47:46 2008
    Info: Elapsed time: 00:00:01