display.vhd

一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
	port(clk:in std_logic;
		mode:in std_logic;
		bcd1: in std_logic_vector(11 downto 0);
		bcd2: in std_logic_vector(11 downto 0);
		bcd: out std_logic_vector(3 downto 0);
		treg1:in std_logic_vector(11 downto 0);
		treg2:in std_logic_vector(11 downto 0);
		sel:in std_logic_vector(1 downto 0);
		lsd:out std_logic_vector(2 downto 0));
end entity;
architecture behav of display is
begin
process(clk)
	variable cnt:integer range 0 to 2;
begin
	if rising_edge(clk) then
		if mode='0' then      --顺计时显示
			case sel is
				when "00" =>	
					if cnt = 0 then
						bcd<= bcd1(3 downto 0);
						lsd <= "100";
						cnt := cnt + 1;
					elsif cnt = 1 then
						bcd<= bcd1(7 downto 4);
						lsd <= "010";
						cnt := cnt + 1;
					elsif cnt = 2 then
						bcd<= bcd1(11 downto 8);
						lsd <= "001";
						cnt := 0;
					end if;
				when "01" =>
					if cnt = 0 then
						bcd<= treg1(3 downto 0);
						lsd <= "100";
						cnt := cnt + 1;
					elsif cnt = 1 then
						bcd<= treg1(7 downto 4);
						lsd <= "010";
						cnt := cnt + 1;
					elsif cnt = 2 then
						bcd<= treg1(11 downto 8);
						lsd <= "001";
						cnt := 0;
					end if;
				when "10" =>
					if cnt = 0 then
						bcd<= treg2(3 downto 0);
						lsd <= "100";
						cnt := cnt + 1;
					elsif cnt = 1 then
						bcd<= treg2(7 downto 4);
						lsd <= "010";
						cnt := cnt + 1;
					elsif cnt = 2 then
						bcd<= treg2(11 downto 8);
						lsd <= "001";
						cnt := 0;
					end if;
				when others =>
					null;
			end case;
			
		else				  --倒计时显示
			if cnt = 0 then
				bcd<= bcd2(3 downto 0);
				lsd <= "100";
				cnt := cnt + 1;
			elsif cnt = 1 then
				bcd<= bcd2(7 downto 4);
				lsd <= "010";
				cnt := cnt + 1;
			elsif cnt = 2 then
				bcd<= bcd2(11 downto 8);
				lsd <= "001";
				cnt := 0;
			end if;
		end if;
	end if;
	
end process;
end behav;