display.inc

一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S

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-- Generated by Quartus II Version 6.0 (Build Build 178 04/27/2006)
-- Created on Sat Mar 01 22:58:11 2008

FUNCTION display (clk, ctime[11..0])
	RETURNS (bcd[3..0], lsd[2..0]);