watch.hier_info

来自「一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要」· HIER_INFO 代码 · 共 461 行

|watch
BELL <= inst7.DB_MAX_OUTPUT_PORT_TYPE
CLK => time:inst.clk
CLK => keyscan:inst8.clk
CLK => display:inst6.clk
RESET => time:inst.reset
RESET => countdown:inst5.reset
KEYIN[0] => keyscan:inst8.keyin[0]
KEYIN[1] => keyscan:inst8.keyin[1]
KEYIN[2] => keyscan:inst8.keyin[2]
KEYIN[3] => keyscan:inst8.keyin[3]
LED1 <= keyscan:inst8.led1
LED2 <= keyscan:inst8.led2
LED3 <= keyscan:inst8.led3
BCD[0] <= display:inst6.bcd0
BCD[1] <= display:inst6.bcd1
BCD[2] <= display:inst6.bcd2
BCD[3] <= display:inst6.bcd3
KEYOUT[0] <= keyscan:inst8.keyout[0]
KEYOUT[1] <= keyscan:inst8.keyout[1]
KEYOUT[2] <= keyscan:inst8.keyout[2]
KEYOUT[3] <= keyscan:inst8.keyout[3]
LSD[0] <= display:inst6.lsd[0]
LSD[1] <= display:inst6.lsd[1]
LSD[2] <= display:inst6.lsd[2]


|watch|countdown:inst5
clkout => \pro1:sel_reg[0].CLK
clkout => \pro1:sel_reg[1].CLK
clkout => \pro1:time_up.CLK
clkout => \pro1:bell_reg.CLK
clkout => \pro1:cnt3[0].CLK
clkout => \pro1:cnt3[1].CLK
clkout => \pro1:cnt3[2].CLK
clkout => \pro1:cnt3[3].CLK
clkout => \pro1:cnt2[0].CLK
clkout => \pro1:cnt2[1].CLK
clkout => \pro1:cnt2[2].CLK
clkout => \pro1:cnt2[3].CLK
clkout => \pro1:cnt1[0].CLK
clkout => \pro1:cnt1[1].CLK
clkout => \pro1:cnt1[2].CLK
clkout => \pro1:cnt1[3].CLK
start => pro1~1.IN1
start => pro1~4.IN0
sel => sel_reg~2.OUTPUTSELECT
sel => sel_reg~3.OUTPUTSELECT
add => cnt1~8.OUTPUTSELECT
add => cnt1~9.OUTPUTSELECT
add => cnt1~10.OUTPUTSELECT
add => cnt1~11.OUTPUTSELECT
add => cnt2~12.OUTPUTSELECT
add => cnt2~13.OUTPUTSELECT
add => cnt2~14.OUTPUTSELECT
add => cnt2~15.OUTPUTSELECT
add => cnt3~16.OUTPUTSELECT
add => cnt3~17.OUTPUTSELECT
add => cnt3~18.OUTPUTSELECT
add => cnt3~19.OUTPUTSELECT
reset => comb~0.OUTPUTSELECT
reset => comb~1.OUTPUTSELECT
reset => comb~2.OUTPUTSELECT
reset => \pro1:bell_reg.ACLR
reset => \pro1:cnt3[0].PRESET
reset => \pro1:cnt3[1].PRESET
reset => \pro1:cnt3[2].ACLR
reset => \pro1:cnt3[3].ACLR
reset => \pro1:cnt2[0].ACLR
reset => \pro1:cnt2[1].ACLR
reset => \pro1:cnt2[2].ACLR
reset => \pro1:cnt2[3].ACLR
reset => \pro1:cnt1[0].ACLR
reset => \pro1:cnt1[1].ACLR
reset => \pro1:cnt1[2].ACLR
reset => \pro1:cnt1[3].ACLR
bell <= \pro1:bell_reg.DB_MAX_OUTPUT_PORT_TYPE
bcd2[0] <= \pro1:cnt1[0].DB_MAX_OUTPUT_PORT_TYPE
bcd2[1] <= \pro1:cnt1[1].DB_MAX_OUTPUT_PORT_TYPE
bcd2[2] <= \pro1:cnt1[2].DB_MAX_OUTPUT_PORT_TYPE
bcd2[3] <= \pro1:cnt1[3].DB_MAX_OUTPUT_PORT_TYPE
bcd2[4] <= \pro1:cnt2[0].DB_MAX_OUTPUT_PORT_TYPE
bcd2[5] <= \pro1:cnt2[1].DB_MAX_OUTPUT_PORT_TYPE
bcd2[6] <= \pro1:cnt2[2].DB_MAX_OUTPUT_PORT_TYPE
bcd2[7] <= \pro1:cnt2[3].DB_MAX_OUTPUT_PORT_TYPE
bcd2[8] <= \pro1:cnt3[0].DB_MAX_OUTPUT_PORT_TYPE
bcd2[9] <= \pro1:cnt3[1].DB_MAX_OUTPUT_PORT_TYPE
bcd2[10] <= \pro1:cnt3[2].DB_MAX_OUTPUT_PORT_TYPE
bcd2[11] <= \pro1:cnt3[3].DB_MAX_OUTPUT_PORT_TYPE


|watch|time:inst
clk => clk1.CLK
clk => \divclk:cnt[0].CLK
clk => \divclk:cnt[1].CLK
clk => \divclk:cnt[2].CLK
clk => \divclk:cnt[3].CLK
clk => \divclk:cnt[4].CLK
clk => \divclk:cnt[5].CLK
reset => \timecount:time_reg[0].ACLR
reset => \timecount:time_reg[1].ACLR
reset => \timecount:time_reg[2].ACLR
reset => \timecount:time_reg[3].ACLR
reset => \timecount:time_reg[4].ACLR
reset => \timecount:time_reg[5].ACLR
reset => \timecount:time_reg[6].ACLR
reset => \timecount:time_reg[7].ACLR
reset => \timecount:time_reg[8].ACLR
reset => \timecount:time_reg[9].ACLR
reset => \timecount:time_reg[10].ACLR
reset => \timecount:time_reg[11].ACLR
start => timecount~1.IN1
stop => timecount~0.IN0
clkout <= clk1.DB_MAX_OUTPUT_PORT_TYPE
bcd1[0] <= \timecount:time_reg[0].DB_MAX_OUTPUT_PORT_TYPE
bcd1[1] <= \timecount:time_reg[1].DB_MAX_OUTPUT_PORT_TYPE
bcd1[2] <= \timecount:time_reg[2].DB_MAX_OUTPUT_PORT_TYPE
bcd1[3] <= \timecount:time_reg[3].DB_MAX_OUTPUT_PORT_TYPE
bcd1[4] <= \timecount:time_reg[4].DB_MAX_OUTPUT_PORT_TYPE
bcd1[5] <= \timecount:time_reg[5].DB_MAX_OUTPUT_PORT_TYPE
bcd1[6] <= \timecount:time_reg[6].DB_MAX_OUTPUT_PORT_TYPE
bcd1[7] <= \timecount:time_reg[7].DB_MAX_OUTPUT_PORT_TYPE
bcd1[8] <= \timecount:time_reg[8].DB_MAX_OUTPUT_PORT_TYPE
bcd1[9] <= \timecount:time_reg[9].DB_MAX_OUTPUT_PORT_TYPE
bcd1[10] <= \timecount:time_reg[10].DB_MAX_OUTPUT_PORT_TYPE
bcd1[11] <= \timecount:time_reg[11].DB_MAX_OUTPUT_PORT_TYPE


|watch|keyscan:inst8
clk => led2~reg0.CLK
clk => led1~reg0.CLK
clk => mode~reg0.CLK
clk => add~reg0.CLK
clk => sell~reg0.CLK
clk => treg2[0]~reg0.CLK
clk => treg2[1]~reg0.CLK
clk => treg2[2]~reg0.CLK
clk => treg2[3]~reg0.CLK
clk => treg2[4]~reg0.CLK
clk => treg2[5]~reg0.CLK
clk => treg2[6]~reg0.CLK
clk => treg2[7]~reg0.CLK
clk => treg2[8]~reg0.CLK
clk => treg2[9]~reg0.CLK
clk => treg2[10]~reg0.CLK
clk => treg2[11]~reg0.CLK
clk => treg1[0]~reg0.CLK
clk => treg1[1]~reg0.CLK
clk => treg1[2]~reg0.CLK
clk => treg1[3]~reg0.CLK
clk => treg1[4]~reg0.CLK
clk => treg1[5]~reg0.CLK
clk => treg1[6]~reg0.CLK
clk => treg1[7]~reg0.CLK
clk => treg1[8]~reg0.CLK
clk => treg1[9]~reg0.CLK
clk => treg1[10]~reg0.CLK
clk => treg1[11]~reg0.CLK
clk => bell~reg0.CLK
clk => stop~reg0.CLK
clk => led3~reg0.CLK
clk => sel[0]~reg0.CLK
clk => sel[1]~reg0.CLK
clk => start~reg0.CLK
clk => pre_state~3.IN1
keyin[0] => Equal0.IN7
keyin[0] => Mux0.IN6
keyin[0] => Mux1.IN7
keyin[0] => Mux2.IN7
keyin[0] => Mux3.IN6
keyin[0] => Mux4.IN6
keyin[0] => Mux5.IN260
keyin[0] => Mux6.IN4
keyin[0] => Mux7.IN4
keyin[0] => Mux8.IN4
keyin[0] => Mux9.IN4
keyin[0] => Mux10.IN4
keyin[0] => Mux11.IN4
keyin[0] => Mux12.IN4
keyin[0] => Mux13.IN4
keyin[0] => Mux14.IN4
keyin[0] => Mux15.IN4
keyin[0] => Mux16.IN4
keyin[0] => Mux17.IN4
keyin[0] => Mux18.IN4
keyin[0] => Mux19.IN4
keyin[0] => Mux20.IN4
keyin[0] => Mux21.IN4
keyin[0] => Mux22.IN4
keyin[0] => Mux23.IN4
keyin[0] => Mux24.IN4
keyin[0] => Mux25.IN4
keyin[0] => Mux26.IN4
keyin[0] => Mux27.IN4
keyin[0] => Mux28.IN4
keyin[0] => Mux29.IN4
keyin[0] => Mux30.IN251
keyin[0] => Mux31.IN251
keyin[0] => Mux32.IN6
keyin[0] => Mux33.IN6
keyin[0] => Mux34.IN6
keyin[1] => Equal0.IN6
keyin[1] => Mux0.IN5
keyin[1] => Mux1.IN6
keyin[1] => Mux2.IN6
keyin[1] => Mux3.IN5
keyin[1] => Mux4.IN5
keyin[1] => Mux5.IN259
keyin[1] => Mux6.IN3
keyin[1] => Mux7.IN3
keyin[1] => Mux8.IN3
keyin[1] => Mux9.IN3
keyin[1] => Mux10.IN3
keyin[1] => Mux11.IN3
keyin[1] => Mux12.IN3
keyin[1] => Mux13.IN3
keyin[1] => Mux14.IN3
keyin[1] => Mux15.IN3
keyin[1] => Mux16.IN3
keyin[1] => Mux17.IN3
keyin[1] => Mux18.IN3
keyin[1] => Mux19.IN3
keyin[1] => Mux20.IN3
keyin[1] => Mux21.IN3
keyin[1] => Mux22.IN3
keyin[1] => Mux23.IN3
keyin[1] => Mux24.IN3
keyin[1] => Mux25.IN3
keyin[1] => Mux26.IN3
keyin[1] => Mux27.IN3
keyin[1] => Mux28.IN3
keyin[1] => Mux29.IN3
keyin[1] => Mux30.IN250
keyin[1] => Mux31.IN250
keyin[1] => Mux32.IN5
keyin[1] => Mux33.IN5
keyin[1] => Mux34.IN5
keyin[2] => Equal0.IN5
keyin[2] => Mux0.IN4
keyin[2] => Mux1.IN5
keyin[2] => Mux2.IN5
keyin[2] => Mux3.IN4
keyin[2] => Mux4.IN4
keyin[2] => Mux5.IN258
keyin[2] => Mux6.IN2
keyin[2] => Mux7.IN2
keyin[2] => Mux8.IN2
keyin[2] => Mux9.IN2
keyin[2] => Mux10.IN2
keyin[2] => Mux11.IN2
keyin[2] => Mux12.IN2
keyin[2] => Mux13.IN2
keyin[2] => Mux14.IN2
keyin[2] => Mux15.IN2
keyin[2] => Mux16.IN2
keyin[2] => Mux17.IN2
keyin[2] => Mux18.IN2
keyin[2] => Mux19.IN2
keyin[2] => Mux20.IN2
keyin[2] => Mux21.IN2
keyin[2] => Mux22.IN2
keyin[2] => Mux23.IN2
keyin[2] => Mux24.IN2
keyin[2] => Mux25.IN2
keyin[2] => Mux26.IN2
keyin[2] => Mux27.IN2
keyin[2] => Mux28.IN2
keyin[2] => Mux29.IN2
keyin[2] => Mux30.IN249
keyin[2] => Mux31.IN249
keyin[2] => Mux32.IN4
keyin[2] => Mux33.IN4
keyin[2] => Mux34.IN4
keyin[3] => Equal0.IN4
keyin[3] => Mux0.IN3
keyin[3] => Mux1.IN4
keyin[3] => Mux2.IN4
keyin[3] => Mux3.IN3
keyin[3] => Mux4.IN3
keyin[3] => Mux5.IN257
keyin[3] => Mux6.IN1
keyin[3] => Mux7.IN1
keyin[3] => Mux8.IN1
keyin[3] => Mux9.IN1
keyin[3] => Mux10.IN1
keyin[3] => Mux11.IN1
keyin[3] => Mux12.IN1
keyin[3] => Mux13.IN1
keyin[3] => Mux14.IN1
keyin[3] => Mux15.IN1
keyin[3] => Mux16.IN1
keyin[3] => Mux17.IN1
keyin[3] => Mux18.IN1
keyin[3] => Mux19.IN1
keyin[3] => Mux20.IN1
keyin[3] => Mux21.IN1
keyin[3] => Mux22.IN1
keyin[3] => Mux23.IN1
keyin[3] => Mux24.IN1
keyin[3] => Mux25.IN1
keyin[3] => Mux26.IN1
keyin[3] => Mux27.IN1
keyin[3] => Mux28.IN1
keyin[3] => Mux29.IN1
keyin[3] => Mux30.IN248
keyin[3] => Mux31.IN248
keyin[3] => Mux32.IN3
keyin[3] => Mux33.IN3
keyin[3] => Mux34.IN3
keyout[0] <= <VCC>
keyout[1] <= reg2~2.DB_MAX_OUTPUT_PORT_TYPE
keyout[2] <= reg2~1.DB_MAX_OUTPUT_PORT_TYPE
keyout[3] <= reg2~0.DB_MAX_OUTPUT_PORT_TYPE
bcd1[0] => Mux17.IN5
bcd1[0] => Mux29.IN5
bcd1[1] => Mux16.IN5
bcd1[1] => Mux28.IN5
bcd1[2] => Mux15.IN5
bcd1[2] => Mux27.IN5
bcd1[3] => Mux14.IN5
bcd1[3] => Mux26.IN5
bcd1[4] => Mux13.IN5
bcd1[4] => Mux25.IN5
bcd1[5] => Mux12.IN5
bcd1[5] => Mux24.IN5
bcd1[6] => Mux11.IN5
bcd1[6] => Mux23.IN5
bcd1[7] => Mux10.IN5
bcd1[7] => Mux22.IN5
bcd1[8] => Mux9.IN5
bcd1[8] => Mux21.IN5
bcd1[9] => Mux8.IN5
bcd1[9] => Mux20.IN5
bcd1[10] => Mux7.IN5
bcd1[10] => Mux19.IN5
bcd1[11] => Mux6.IN5
bcd1[11] => Mux18.IN5
treg1[0] <= treg1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[1] <= treg1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[2] <= treg1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[3] <= treg1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[4] <= treg1[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[5] <= treg1[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[6] <= treg1[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[7] <= treg1[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[8] <= treg1[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[9] <= treg1[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[10] <= treg1[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[11] <= treg1[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[0] <= treg2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[1] <= treg2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[2] <= treg2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[3] <= treg2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[4] <= treg2[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[5] <= treg2[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[6] <= treg2[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[7] <= treg2[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[8] <= treg2[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[9] <= treg2[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[10] <= treg2[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg2[11] <= treg2[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[0] <= sel[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[1] <= sel[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
start <= start~reg0.DB_MAX_OUTPUT_PORT_TYPE
stop <= stop~reg0.DB_MAX_OUTPUT_PORT_TYPE
mode <= mode~reg0.DB_MAX_OUTPUT_PORT_TYPE
sell <= sell~reg0.DB_MAX_OUTPUT_PORT_TYPE
led1 <= led1~reg0.DB_MAX_OUTPUT_PORT_TYPE
led2 <= led2~reg0.DB_MAX_OUTPUT_PORT_TYPE
led3 <= led3~reg0.DB_MAX_OUTPUT_PORT_TYPE
add <= add~reg0.DB_MAX_OUTPUT_PORT_TYPE
bell <= bell~reg0.DB_MAX_OUTPUT_PORT_TYPE


|watch|display:inst6
clk => lsd[0]~reg0.CLK
clk => lsd[1]~reg0.CLK
clk => lsd[2]~reg0.CLK
clk => bcd[0]~reg0.CLK
clk => bcd[1]~reg0.CLK
clk => bcd[2]~reg0.CLK
clk => bcd[3]~reg0.CLK
clk => cnt[0].CLK
clk => cnt[1].CLK
mode => process0~0.IN0
bcd1[0] => bcd~11.DATAB
bcd1[1] => bcd~10.DATAB
bcd1[2] => bcd~9.DATAB
bcd1[3] => bcd~8.DATAB
bcd1[4] => bcd~7.DATAB
bcd1[5] => bcd~6.DATAB
bcd1[6] => bcd~5.DATAB
bcd1[7] => bcd~4.DATAB
bcd1[8] => bcd~3.DATAB
bcd1[9] => bcd~2.DATAB
bcd1[10] => bcd~1.DATAB
bcd1[11] => bcd~0.DATAB
bcd2[0] => bcd~47.DATAB
bcd2[1] => bcd~46.DATAB
bcd2[2] => bcd~45.DATAB
bcd2[3] => bcd~44.DATAB
bcd2[4] => bcd~43.DATAB
bcd2[5] => bcd~42.DATAB
bcd2[6] => bcd~41.DATAB
bcd2[7] => bcd~40.DATAB
bcd2[8] => bcd~39.DATAB
bcd2[9] => bcd~38.DATAB
bcd2[10] => bcd~37.DATAB
bcd2[11] => bcd~36.DATAB
bcd[0] <= bcd[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bcd[1] <= bcd[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bcd[2] <= bcd[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bcd[3] <= bcd[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
treg1[0] => bcd~23.DATAB
treg1[1] => bcd~22.DATAB
treg1[2] => bcd~21.DATAB
treg1[3] => bcd~20.DATAB
treg1[4] => bcd~19.DATAB
treg1[5] => bcd~18.DATAB
treg1[6] => bcd~17.DATAB
treg1[7] => bcd~16.DATAB
treg1[8] => bcd~15.DATAB
treg1[9] => bcd~14.DATAB
treg1[10] => bcd~13.DATAB
treg1[11] => bcd~12.DATAB
treg2[0] => bcd~35.DATAB
treg2[1] => bcd~34.DATAB
treg2[2] => bcd~33.DATAB
treg2[3] => bcd~32.DATAB
treg2[4] => bcd~31.DATAB
treg2[5] => bcd~30.DATAB
treg2[6] => bcd~29.DATAB
treg2[7] => bcd~28.DATAB
treg2[8] => bcd~27.DATAB
treg2[9] => bcd~26.DATAB
treg2[10] => bcd~25.DATAB
treg2[11] => bcd~24.DATAB
sel[0] => Mux0.IN5
sel[0] => Mux1.IN5
sel[0] => Mux2.IN5
sel[0] => Mux3.IN5
sel[0] => Mux4.IN4
sel[0] => Mux5.IN4
sel[0] => Mux6.IN4
sel[0] => Mux7.IN4
sel[0] => Mux8.IN4
sel[1] => Mux0.IN4
sel[1] => Mux1.IN4
sel[1] => Mux2.IN4
sel[1] => Mux3.IN4
sel[1] => Mux4.IN3
sel[1] => Mux5.IN3
sel[1] => Mux6.IN3
sel[1] => Mux7.IN3
sel[1] => Mux8.IN3
lsd[0] <= lsd[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lsd[1] <= lsd[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lsd[2] <= lsd[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE