watch.smp_dump.txt

一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S

State Machine - |watch|keyscan:inst8|pre_state
Name pre_state.state_bit_1 pre_state.state_bit_0 
pre_state.s0 0 0 
pre_state.s1 0 1 
pre_state.s2 1 0