watch.db_info

一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S

Quartus_Version = Version 6.0 Build 178 04/27/2006 SJ Full Version
Version_Index = 67154432
Creation_Time = Sat Mar 01 20:59:16 2008