watch.fit.rpt
来自「一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要」· RPT 代码 · 共 453 行 · 第 1/5 页
RPT
453 行
; time:inst|\timecount:time_reg[10] ; 5 ;
; time:inst|\divclk:cnt[5] ; 5 ;
; time:inst|\divclk:cnt[4] ; 5 ;
; display:inst6|bcd[3] ; 3 ;
; time:inst|\timecount:time_reg[11] ; 3 ;
+-------------------------------------------+---------+
+-------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+--------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+--------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 163 / 288 ( 57 % ) ;
; PIAs ; 190 / 288 ( 66 % ) ;
+----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 23.75) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 0 ;
; 12 - 14 ; 0 ;
; 15 - 17 ; 1 ;
; 18 - 20 ; 1 ;
; 21 - 23 ; 1 ;
; 24 - 26 ; 2 ;
; 27 - 29 ; 2 ;
; 30 - 32 ; 1 ;
+-----------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+-----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 14.13) ; Number of LABs (Total = 8) ;
+-----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 6 ;
+-----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 17 ;
; 2 ; 4 ;
+--------------------------+------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC8 ; CLK, keyscan:inst8|Mux30~288, watch|keyscan:inst8|pre_state.state_bit_0, KEYIN[2], KEYIN[3], KEYIN[1], KEYIN[0], keyscan:inst8|sell, watch|keyscan:inst8|pre_state.state_bit_1 ; keyscan:inst8|sell, countdown:inst5|\pro1:sel_reg[0], countdown:inst5|\pro1:sel_reg[1], countdown:inst5|\pro1:cnt1[0], countdown:inst5|\pro1:cnt1[1], countdown:inst5|\pro1:cnt1[2], countdown:inst5|\pro1:cnt1[3], countdown:inst5|\pro1:cnt2[0], countdown:inst5|\pro1:cnt2[1], countdown:inst5|\pro1:cnt2[2], countdown:inst5|\pro1:cnt2[3], countdown:inst5|\pro1:cnt3[0], countdown:inst5|\pro1:cnt3[1], countdown:inst5|\pro1:cnt3[2], countdown:inst5|\pro1:cnt3[3], keyscan:inst8|Mux30~288, countdown:inst5|\pro1:cnt1[1]~22, countdown:inst5|\pro1:cnt1[3]~13, countdown:inst5|\pro1:cnt2[1]~22, countdown:inst5|\pro1:cnt2[3]~13, countdown:inst5|\pro1:cnt3[1]~418, countdown:inst5|\pro1:cnt3[3]~608 ;
; A ; LC11 ; CLK, watch|keyscan:inst8|pre_state.state_bit_0, KEYIN[2], KEYIN[3], KEYIN[1], KEYIN[0], watch|keyscan:inst8|pre_state.state_bit_1 ; keyscan:inst8|led3, watch|keyscan:inst8|pre_state.state_bit_0, watch|keyscan:inst8|pre_state.state_bit_1, keyscan:inst8|pre_state.s0~15, watch|keyscan:inst8|pre_state.state_bit_1~52, keyscan:inst8|led1, keyscan:inst8|led2, keyscan:inst8|bell, keyscan:inst8|sel[0], keyscan:inst8|sel[1], keyscan:inst8|add, keyscan:inst8|sell, keyscan:inst8|treg2[0], keyscan:inst8|treg1[0], keyscan:inst8|treg2[1], keyscan:inst8|treg1[1], keyscan:inst8|treg2[2], keyscan:inst8|treg1[2], keyscan:inst8|treg2[3], keyscan:inst8|treg1[3], keyscan:inst8|treg2[4], keyscan:inst8|treg1[4], keyscan:inst8|treg2[5], keyscan:inst8|treg1[5], keyscan:inst8|treg2[6], keyscan:inst8|treg1[6], keyscan:inst8|treg2[7], keyscan:inst8|treg1[7], keyscan:inst8|treg2[8], keyscan:inst8|treg1[8], keyscan:inst8|treg2[9], keyscan:inst8|treg1[9], keyscan:inst8|treg2[10], keyscan:inst8|treg1[10], keyscan:inst8|treg2[11], keyscan:inst8|treg1[11], keyscan:inst8|Mux31~347, keyscan:inst8|Mux30~288 ;
; A ; LC14 ; CLK, time:inst|\timecount:time_reg[2], watch|keyscan:inst8|pre_state.state_bit_0, watch|keyscan:inst8|pre_state.state_bit_1, KEYIN[1], KEYIN[0], KEYIN[2], KEYIN[3] ; display:inst6|bcd~5300 ;
; A ; LC5 ; CLK, KEYIN[2], KEYIN[3], watch|keyscan:inst8|pre_state.state_bit_1, KEYIN[1], KEYIN[0], keyscan:inst8|led1 ; keyscan:inst8|led1, LED1, display:inst6|cnt[1], display:inst6|cnt[0], display:inst6|lsd[0], display:inst6|lsd[1], display:inst6|lsd[2], display:inst6|bcd~5288, display:inst6|bcd[1], display:inst6|bcd~5300, display:inst6|bcd[2], display:inst6|bcd[3], display:inst6|bcd~5313, display:inst6|bcd~5319, display:inst6|bcd~5325, display:inst6|bcd~5330, display:inst6|bcd~5269sexp2bal, display:inst6|bcd~5276bal, display:inst6|bcd~5275sexp2bal ;
; A ; LC3 ; CLK, KEYIN[2], KEYIN[3], watch|keyscan:inst8|pre_state.state_bit_1, KEYIN[1], KEYIN[0], keyscan:inst8|led2 ; keyscan:inst8|led2, LED2 ;
; A ; LC6 ; CLK, watch|keyscan:inst8|pre_state.state_bit_1, KEYIN[1], KEYIN[0], KEYIN[2], KEYIN[3] ; inst7~0 ;
; A ; LC13 ; CLK, time:inst|\timecount:time_reg[2], watch|keyscan:inst8|pre_state.state_bit_0, watch|keyscan:inst8|pre_state.state_bit_1, KEYIN[1], KEYIN[0], KEYIN[2], KEYIN[3] ; display:inst6|bcd~5300 ;
; A ; LC7 ; watch|keyscan:inst8|pre_state.state_bit_0, KEYIN[2], KEYIN[3], KEYIN[1], KEYIN[0], keyscan:inst8|sell, watch|keyscan:inst8|pre_state.state_bit_1 ; keyscan:inst8|sell ;
; A ; LC2 ; CLK, keyscan:inst8|Mux31~347, watch|keyscan:inst8|pre_state.state_bit_0, KEYIN[2], KEYIN[3], KEYIN[1], KEYIN[0], keyscan:inst8|add, watch|keyscan:inst8|pre_state.state_bit_1 ; keyscan:inst8|add, countdown:inst5|\pro1:cnt1[0], countdown:inst5|\pro1:cnt1[1], countdown:inst5|\pro1:cnt1[2], countdown:inst5|\pro1:cnt1[3], countdown:inst5|\pro1:cnt2[0], countdown:inst5|\pro1:cnt2[1], countdown:inst5|\pro1:cnt2[2], countdown:inst5|\pro1:cnt2[3], countdown:inst5|\pro1:cnt3[0], countdown:inst5|\pro1:cnt3[1], countdown:inst5|\pro1:cnt3[2], countdown:inst5|\pro1:cnt3[3], keyscan:inst8|Mux31~347, countdown:inst5|\pro1:cnt1[1]~22, countdown:inst5|\pro1:cnt1[3]~13, countdown:inst5|\pro1:cnt2[1]~22, countdown:inst5|\pro1:cnt2[3]~13, countdown:inst5|\pro1:cnt3[1]~418, countdown:inst5|\pro1:cnt3[3]~608 ;
; A ; LC4 ; CLK, time:inst|\timecount:time_reg[6], watch|keyscan:inst8|pre_state.state_bit_0, watch|keyscan:inst8|pre_state.state_bit_1, KEYIN[1], KEYIN[0], KEYIN[2], KEYIN[3] ; display:inst6|bcd~5300
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