keyscan.vhd

一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity keyscan is
port(clk:in std_logic;                      --时钟频率500Hz
	keyin:in std_logic_vector(3 downto 0);  -- 键盘输出信号
	keyout:out std_logic_vector(3 downto 0):="0111";
	                                        --键盘扫描信号
	bcd1:in std_logic_vector(11 downto 0);
	treg1:out std_logic_vector(11 downto 0);
	treg2:out std_logic_vector(11 downto 0);
	sel:out std_logic_vector(1 downto 0);
	start:out std_logic;
	stop:out std_logic;
	mode:out std_logic;     
	sell:out std_logic;
	led1:out std_logic;
	led2:out std_logic;
	led3:out std_logic;
	add:out std_logic;               
	bell:out std_logic);
end entity;
architecture behav of keyscan is 
	type state_type is (s0,s1,s2);
	signal pre_state ,next_state:state_type:=s0;
	signal reg2:std_logic_vector(3 downto 0);
begin 
	pro1:process(clk)
	begin
		if rising_edge(clk) then 
			if keyin="1111" then
				pre_state<=next_state;
			end if;
		end if;
	end process pro1;
	pro2:process(pre_state,keyin)
	begin
		case pre_state is
			when s0 =>
				reg2<="0111";
				next_state<=s1;
			when s1 =>
				reg2<="1011";
				next_state<=s2;
			when s2 =>
				reg2<="1101";
				next_state<=s0;
		end case;
	end process pro2;
	--进程pro3对扫描结果编码，只扫描0111和1011这两排
	pro3:process(clk,keyin,reg2)
	begin
		if rising_edge(clk) then 
			case reg2&keyin is
				when "01110111"=>
					start<='1';
					sel<="00";
					led3<='1';
					stop<='0';
					bell<='1';  
				when "01111011"=>
					treg1<=bcd1;
					bell<='1'; 
				when "01111101"=>
					treg2<=bcd1;
					bell<='1';  
				when "01111110"=>
					bell<='1';  
					start<='0';
					stop<='1';
					led3<='0';		  
				when "10110111"=>
					sel<="01";
					bell<='1';  --按键s7   显示记录时间
				when "10111011"=>
					bell<='1';  --按键s8  
					sel<="10";				
				when "10111101"=>
					bell<='1';  --按键s9   选择设置时间位
					sell<='1'; 
				when "10111110"=>
					bell<='1';  --按键s10  设置时间加一
					add<='1';
				when "11010111"=>
					bell<='1';
					mode<='0';
					led1<='1';
					led2<='0';		
				when "11011011"=>
					bell<='1';
					mode<='1';
					led2<='1';
					led1<='0'; 
				when others =>
					bell<='0';
					add<='0';
					sell<='0';
			end case;
		end if;
	end process pro3;
	keyout<=reg2;
end behav;