watch.tan.summary

一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 12.000 ns
From           : KEYIN[0]
To             : keyscan:inst8|sell
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 26.000 ns
From           : countdown:inst5|bell
To             : BELL
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 6.000 ns
From           : RESET
To             : countdown:inst5|\pro1:time_up
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 31.25 MHz ( period = 32.000 ns )
From           : time:inst|\timecount:time_reg[10]
To             : display:inst6|bcd[2]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Hold: 'CLK'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : keyscan:inst8|led3
To             : countdown:inst5|\pro1:sel_reg[0]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 54

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 54

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