watch.fit.summary

一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S

Fitter Status : Successful - Wed Mar 12 01:20:13 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : watch
Top-level Entity Name : watch
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Final
Total macrocells : 113 / 128 ( 88 % )
Total pins : 25 / 68 ( 37 % )