cpu.v

以前在学校里的课程设计

module mainboard(data_inout,address_out,S,R,D,clk,reset);
    parameter width=8;
    inout [width-1:0] data_inout;   
    output [width-1:0] address_out;       
    output S;                  
    output R;                  
    output D;                  
    wire  [width-1:0]  data_in;     

    input  clk;                 
    input  reset;               

    wire [width-1:0] data_bus;//????  
    wire [width-1:0] ALU_out;   
    wire [width-1:0] GR_out;    
    wire [width-1:0] IR_out;          
    wire [width-1:0] AC_out;          
    wire is_zero;               
    wire C_out;                 
    wire C_in;                  
    wire Z_out;                 
   

    wire [width-1:0] AR_address;      
    wire [width-1:0] PC_address;      
    wire [2:0] GR_address;      


    wire [4:0] ALU_OP;         
    wire [1:0] mux_C_sel;      
    wire [1:0] mux_DB_sel;     
    wire [1:0] mux_AB_sel;     
    
    wire CLE;                  
    wire ZLE;                   
    wire IRLE;                
    wire ARLE;                 
    wire ACLE;                 
    wire GRLE;                  
    wire PCLE;                  
    wire PCCE;                  
    wire ALU_C;                 
                     
    assign data_in=data_inout;   
    assign data_inout =(S & R)? data_bus: 'bz;
                                 
    assign is_zero=(ALU_out == 'b0)?'b1:'b0;
                                
    
    register #(1) C  (.register_out(C_out),.register_in(C_in),.clk(clk),
                      .reset(reset),.load_enable(CLE)); 
    register #(1) Z  (.register_out(Z_out),.register_in(is_zero),.clk(clk),
                      .reset(reset),.load_enable(ZLE)); 
    register #(8) IR (.register_out(IR_out),.register_in(data_bus),.clk(clk),
                      .reset(reset),.load_enable(IRLE));
    register #(8) AR (.register_out(AR_address),.register_in(data_bus),.clk(clk),
                      .reset(reset),.load_enable(ARLE));            
    register #(8) AC (.register_out(AC_out),.register_in(data_bus),.clk(clk),
                      .reset(reset),.load_enable(ACLE));
                                                                                                                                                                                      
    mux4 #(1) mux_C  (.mux4_out(C_in),.m0_in(ALU_C),.m1_in(AC_out[0]),.m2_in(AC_out[7]),
                      .m3_in(1'b0),.sel_in(mux_C_sel)); 
    mux4 #(8) mux_DB (.mux4_out(data_bus),.m0_in(AC_out),.m1_in(ALU_out),
                      .m2_in(data_in),.m3_in(8'b0),.sel_in(mux_DB_sel));
    mux2 #(8) mux_AB (.mux2_out(address_out),.m0_in(PC_address),.m1_in(AR_address),
                      .sel_in(mux_AB_sel));
 
    GR  GR  (.GR_out(GR_out),.GR_in(data_bus),.clk(clk),.reset(reset),
             .GR_address(GR_address),.load_enable(GRLE));

    ALU ALU (.ALU_O(ALU_out),.ALU_C(ALU_C),.C_in(C_out),.op(ALU_OP),
             .AC_in(AC_out),.GR_in(GR_out));

    PC  PC  (.pc_out(PC_address),.pc_in(data_bus),.clk(clk),.reset(reset),
             .load_enable(PCLE),.count_enable(PCCE));
              
    CU  CU  (.CLE(CLE),.ZLE(ZLE),.ALU_OP(ALU_OP),.ACLE(ACLE),.GR_address(GR_address),
             .GRLE(GRLE),.IRLE(IRLE),.ARLE(ARLE),.PCLE(PCLE),.PCCE(PCCE),.mux_C_sel(mux_C_sel),
             .mux_DB_sel(mux_DB_sel),.mux_AB_sel(mux_AB_sel),.S(S),.R(R),.D(D),.clk(clk),
             .reset(reset),.C_in(C_out),.Z_in(Z_out),.IR_in(IR_out));
endmodule