cu.v

以前在学校里的课程设计

module CU (CLE,ZLE,ALU_OP,ACLE,GR_address,GRLE,IRLE,ARLE,PCLE,PCCE,
           mux_C_sel,mux_DB_sel,mux_AB_sel,S,D,R,clk,reset,C_in,Z_in,IR_in);
   
   parameter FIRST = 'b00,SECOND = 'b01,THIRD = 'b10,HLT = 'b11;       
    
     
   output CLE;    reg CLE;         
   output ZLE;    reg ZLE;         
   output ACLE;   reg ACLE;        
   output GRLE;   reg GRLE;      
   output ARLE;   reg ARLE;        
   output IRLE;   reg IRLE;        
   output PCLE;   reg PCLE;        
   output PCCE;   reg PCCE;        

   output [3:0] ALU_OP;      reg [4:0] ALU_OP;      
   output [2:0] GR_address;  reg [2:0] GR_address;  
   output [1:0] mux_C_sel;   reg [1:0] mux_C_sel;   
   output [1:0] mux_DB_sel;  reg [1:0] mux_DB_sel;  
   output [1:0] mux_AB_sel;  reg [1:0] mux_AB_sel;  
   output S;            reg S;            
   output D;            reg D;            
   output R;            reg R;            
      
 //???????
   input  clk;              
   input  reset;           
   input  C_in;             
   input  Z_in;            
   input  [7:0]  IR_in;     
      
   reg [1:0] state; 

   always @(posedge clk or negedge reset) 
       begin
          if(!reset) 
                state <=FIRST; 
          else begin
                case(state)
                FIRST:state <= SECOND; //FIST-->SECOND
                SECOND:state <=THIRD;  //SECOD-->THIRD
                THIRD:if (IR_in[7:3] == 'b11111) // HTL??
                                state <= HLT;
                      else
                                state <=FIRST;    //THIRD-->FIRST
                HLT:state <= HLT;      //????????
                endcase
          end
       end

   always @(state or C_in or Z_in or IR_in) //????????
      begin

        CLE = 'b0;    
        ZLE = 'b0;
        ALU_OP = 'b0;
        ACLE = 'b0;
        GR_address = 'b0;
        GRLE = 'b0;
        IRLE = 'b0;
        ARLE = 'b0;
        PCLE = 'b0;
        PCCE = 'b0;

        mux_C_sel = 'b0;
        mux_DB_sel = 2'b00;
        mux_AB_sel = 2'b00;
        S='b0;
        R='b0;
        D='b0;
        

        case(state) 
        FIRST:
        begin           
                mux_AB_sel = 'b00;           
                mux_DB_sel = 'b10; 
                S='b1;        
                D='b1;        
                IRLE = 'b1;        
                PCCE = 'b1;      
        end
        SECOND:
        begin //???????

           case(IR_in[7:3])
                          
                //????? ?L/S??
                'b00000: // Mi->AC
                    begin                               
                       mux_AB_sel = 'b00;  //??????PC 
                       mux_DB_sel = 'b10;  //????????????  
                       PCCE = 'b1;         //PC????
                       S='b1;         //??????         
                       D='b1;         //???
                       ARLE = 'b1;         //???????                   
                    end 
                    
                 'b00001: //MOV Mi,AC
                    begin                               
                       mux_AB_sel = 'b00; 
                       mux_DB_sel = 'b10; 
                       PCCE = 'b1;        
                       S='b1;             
                       D='b1;        
                       ARLE = 'b1;                              
                    end
                                      
                  'b00011://MOV RI,AC
                      begin
                        GR_address = IR_in[2:0];  
                        ALU_OP = IR_in[7:3];      
                        mux_DB_sel = 'b01;        
                        GRLE = 'b1;               
                        CLE = 'b1;                
                        ZLE = 'b1;                

                      end
                      
                  'b00100://MOV AC,RI           
                    begin
                        GR_address=IR_in[2:0];    
                        ALU_OP  =  IR_in[7:3];   
                    end
                                                         
                  'b00111, //ADD AC,RI 
                  'b01000,  //SUB AC,RI
                  'b01011,  //ADDC AC,RI
                  'b01100,  //SUBC AC,RI
                  
                  'b01111,  //NOT AC
                  
                  'b11100,
                  'b11101,//* /?
                  
                  'b10000,  //SHCR AC,RI  ??C???????
                  'b10001:  //SHCL AC,RI  ??C???????
                  
                    begin
                        GR_address = IR_in[2:0]; 
                        ALU_OP  =    IR_in[7:3]; 
                        CLE='b1;            
                    end 
                                              
                  'b10110:         //JMP MI
                     begin
                       mux_AB_sel = 'b00;  
                       mux_DB_sel = 'b10; 
                       PCCE = 'b1;        
                       S='b1;               
                       D='b1;        
                       PCLE = 'b1;        
                     end
                     
                  'b10111:         //JNZ MI   //JZ
                     begin
                       mux_AB_sel = 'b00;  
                       mux_DB_sel = 'b10; 
                       PCCE = 'b1;        
                       S='b1;        
                       D='b1;       
                      case(IR_in[0])
                      'b1:
                       begin

                        if(!Z_in)         //?Z_in!=0,??
                           begin
                            PCLE='b1;     
                           end
                        end
                       'b0:
                         if(Z_in)
                         begin
                           PCLE='b1;
                         end
                        endcase
                     end
                  'b11000:         //JNC MI     //JC
                     begin
                       mux_AB_sel = 'b00;  
                       mux_DB_sel = 'b10; 
                       PCCE = 'b1;       
                       S='b1;         
                       D='b1;       
                       case(IR_in[0])
                       'b1:
                        begin  
                         if(!C_in)          
                           PCLE='b1;      
                         end
                       'b0:
                         begin
                          if(C_in)
                           PCLE='b1;
                         end
                         endcase                      
                     end                               
               endcase
         end
         
       //?????                
       THIRD:
       begin 
          case(IR_in[7:3])
           //????? ?L/S??
          'b00000:     //MOV AC,MI
              begin
              mux_AB_sel='b01;              
              mux_DB_sel='b10;               
              S='b1;                   
              D='b1;                  
              ACLE='b1;                   
              end
              
          'b00001:   //MOV  MI,AC
              begin
              mux_DB_sel='b00;            
              mux_AB_sel='b01;           
              S='b1;                 
              R='b1;               
              end
                     
          'b00011:      //MOV RI,AC
              begin
                 mux_DB_sel='b01;     
                 GRLE='b1;            
                 ZLE = 'b1;          
              end
          'b00100:      //MOV AC,RI
              begin
                 mux_DB_sel='b01;     
                 ACLE='b1;           
                 CLE = 'b1;           
                 ZLE = 'b1;          
              end

              
            'b00111, //ADD AC,RI 
            'b01000,  //SUB AC,RI
            'b01011,  //ADDC AC,RI
            'b01100,  //SUBC AC,RI
                  
            'b01111,  //NOT AC
            
            'b11100,
            'b11101,
                  
            'b10000,  //SHCR AC,RI  
            'b10001:  //SHCL AC,RI  
              begin
                 mux_DB_sel='b01;   
                 ACLE='b1;          
                 ZLE='b1;           
              end                
       endcase
     end           
    endcase   
   end    
endmodule