gr.v

以前在学校里的课程设计

module GR(GR_out,GR_in,clk,reset,GR_address,load_enable);
   parameter width=8;
    
   output [width-1:0] GR_out; 
   input  [width-1:0] GR_in;  
   input  clk;                
   input  reset;             
   input  [2:0] GR_address;   
   input  load_enable;        
   reg   [width-1:0] GR_out;
   reg   [width-1:0] register[7:0];
              
   always @(posedge clk or negedge reset) 
      begin
	 if(!reset)begin	    
            register[0]='b0;
            register[1]='b0;
            register[2]='b0;
            register[3]='b0;
            register[4]='b0;
            register[5]='b0;
            register[6]='b0;
            register[7]='b0;  
	 end		
	 else if(load_enable)        
	    begin
	        case(GR_address)
	         'b000:register[0]<=GR_in;
		 'b001:register[1]<=GR_in;
		 'b010:register[2]<=GR_in;
		 'b011:register[3]<=GR_in;
	         'b100:register[4]<=GR_in;
		 'b101:register[5]<=GR_in;
		 'b110:register[6]<=GR_in;
		 'b111:register[7]<=GR_in;	
		 endcase
	 end
   end

   always @(GR_address or register[0] or register[1] or register[2] or register[3] 
            or register[4] or register[5] or register[6] or register[7])//????
       begin
	 case(GR_address)
	   'b000:GR_out=register[0];
	   'b001:GR_out=register[1];
	   'b010:GR_out=register[2];
	   'b011:GR_out=register[3];
	   'b100:GR_out=register[4];
	   'b101:GR_out=register[5];
	   'b110:GR_out=register[6];
	   'b111:GR_out=register[7];
	endcase
   end
endmodule