clocktop.syr

一个在Xilinx spartan3实现的时钟

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: clocktop.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : clocktop.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : clocktop
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : clocktop
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : clocktop.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "shake.v"
Module <noshake> compiled
Compiling source file "clockcore.v"
Module <clockcore> compiled
Compiling source file "clocktop.v"
Module <clocktop> compiled
No errors in compilation
Analysis of file <clocktop.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clocktop>.
Module <clocktop> is correct for synthesis.
 
Analyzing module <noshake>.
Module <noshake> is correct for synthesis.
 
Analyzing module <clockcore>.
WARNING:Xst:905 - clockcore.v line 163: The signals <screen> are missing in the sensitivity list of always block.
Module <clockcore> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clockcore>.
    Related source file is clockcore.v.
WARNING:Xst:646 - Signal <yearten<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <yearls<3:2>> is assigned but never used.
WARNING:Xst:646 - Signal <monthmsb<3:1>> is assigned but never used.
    Found finite state machine <FSM_0> for signal <screen>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 4                                              |
    | Inputs             | 0                                              |
    | Outputs            | 3                                              |
    | Clock              | b4 (falling_edge)                              |
    | Reset              | b1 (negative)                                  |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 6                                              |
    | Inputs             | 1                                              |
    | Outputs            | 5                                              |
    | Clock              | b3 (falling_edge)                              |
    | Reset              | b1 (negative)                                  |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x1-bit ROM for signal <dot>.
    Found 4-bit adder for signal <$n0049> created at line 284.
    Found 4-bit adder for signal <$n0050> created at line 295.
    Found 4-bit comparator equal for signal <$n0105> created at line 318.
    Found 4-bit comparator equal for signal <$n0106> created at line 318.
    Found 4-bit comparator not equal for signal <$n0108> created at line 318.
    Found 4-bit comparator not equal for signal <$n0109> created at line 318.
    Found 4-bit adder for signal <$n0114> created at line 323.
    Found 4-bit adder for signal <$n0124> created at line 341.
    Found 4-bit adder for signal <$n0134> created at line 309.
    Found 1-bit xor2 for signal <$n0170> created at line 85.
    Found 1-bit xor3 for signal <bigmonth>.
    Found 4-bit up counter for signal <day<1>>.
    Found 4-bit register for signal <day<0>>.
    Found 1-bit register for signal <dayc>.
    Found 4-bit 16-to-1 multiplexer for signal <dispdata>.
    Found 26-bit up counter for signal <divcounter>.
    Found 1-bit register for signal <hclk>.
    Found 4-bit up counter for signal <hour<1>>.
    Found 4-bit register for signal <hour<0>>.
    Found 1-bit register for signal <mclk>.
    Found 4-bit register for signal <min<1>>.
    Found 4-bit up counter for signal <min<0>>.
    Found 1-bit register for signal <monc>.
    Found 4-bit up counter for signal <month<1>>.
    Found 4-bit register for signal <month<0>>.
    Found 1-of-4 decoder for signal <ptmp>.
    Found 11-bit up counter for signal <scan>.
    Found 1-bit register for signal <sclk>.
    Found 4-bit register for signal <sec<1>>.
    Found 4-bit up counter for signal <sec<0>>.
    Found 4-bit up counter for signal <year>.
    Found 1-bit register for signal <year1c>.
    Found 1-bit register for signal <year2c>.
    Found 1-bit register for signal <year3c>.
    Found 1-bit register for signal <year4c>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred  11 Counter(s).
	inferred  13 D-type flip-flop(s).
	inferred   5 Adder/Subtracter(s).
	inferred   4 Comparator(s).
	inferred  12 Multiplexer(s).
	inferred   1 Decoder(s).
	inferred   1 Xor(s).
Unit <clockcore> synthesized.


Synthesizing Unit <noshake>.
    Related source file is shake.v.
WARNING:Xst:1780 - Signal <counten> is never used or assigned.
    Found 1-bit register for signal <noshakeb2>.
    Found 1-bit register for signal <noshakeb3>.
    Found 1-bit register for signal <noshakeb4>.
    Found 1-bit register for signal <sample>.
    Found 21-bit up counter for signal <shakecount>.
    Summary:
	inferred   1 Counter(s).
	inferred   4 D-type flip-flop(s).
Unit <noshake> synthesized.


Synthesizing Unit <clocktop>.
    Related source file is clocktop.v.
Unit <clocktop> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 2
# ROMs                             : 1
  16x1-bit ROM                     : 1
# Registers                        : 18
  4-bit register                   : 5
  1-bit register                   : 13
# Counters                         : 12
  11-bit up counter                : 1
  21-bit up counter                : 1
  26-bit up counter                : 1