📄 clocktop.mrp
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Release 6.1i Map G.23Xilinx Mapping Report File for Design 'clocktop'Design Information------------------Command Line : D:/Xilinx/bin/nt/map.exe -intstyle ise -p xc3s400-pq208-4 -cm
area -pr b -k 4 -c 100 -tx off -o clocktop_map.ncd clocktop.ngd clocktop.pcf Target Device : x3s400Target Package : pq208Target Speed : -4Mapper Version : spartan3 -- $Revision: 1.16 $Mapped Date : Wed Aug 01 22:11:10 2007Design Summary--------------Number of errors: 0Number of warnings: 9Logic Utilization: Number of Slice Flip Flops: 135 out of 7,168 1% Number of 4 input LUTs: 250 out of 7,168 3%Logic Distribution: Number of occupied Slices: 143 out of 3,584 3% Number of Slices containing only related logic: 143 out of 143 100% Number of Slices containing unrelated logic: 0 out of 143 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 261 out of 7,168 3% Number used as logic: 250 Number used as a route-thru: 11 Number of bonded IOBs: 17 out of 141 12% IOB Flip Flops: 1 Number of GCLKs: 1 out of 8 12%Total equivalent gate count for design: 3,020Additional JTAG gate count for IOBs: 816Peak Memory Usage: 75 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_mclkbuf
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_sclkbuf
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_moncbuf
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_daycbuf
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_y1buf is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_y2buf is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_y3buf is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_y4buf is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_hclkbuf
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| N<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || P<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || P<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || P<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || P<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || b1 | IOB | INPUT | LVCMOS25 | | | | | || b2 | IOB | INPUT | LVCMOS25 | | | | | || b3 | IOB | INPUT | LVCMOS25 | | | | | || b4 | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || clk | IOB | INPUT | LVCMOS25 | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.⌨️ 快捷键说明
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